Boundary-scan circuit for use with linearized impedance control

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3241581, G01R 3128

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active

058927786

ABSTRACT:
A circuit for coupling a LIC driver to a IEEE 1149.1 boundary scan implementation includes a logic circuit that converts the data and oe signals of the IEEE 1149.1 specification to test "q.sub.-- up" and "q.sub.-- dn" signals meeting the requirements of the LIC driver. These test "q.sub.-- up" and "q.sub.-- dn" signals are selectively provided to the LIC driver during boundary scan testing of the output driver. In a further refinement, the logic circuit also converts functional q.sub.-- up and q.sub.-- dn signals provided by the circuit under test to the data and oe signals of the IEEE 1149.1 specification. The logic circuit allows the widely used IEEE 1149.1 boundary scan standard to be used with LIC drivers. The resulting compatibility simplifies the testing and use of the LIC drivers, and provides a new boundary scan standard for use with LIC drivers that is compliant with the IEEE 1149.1 standard.

REFERENCES:
patent: 5012185 (1991-04-01), Ohfuji
patent: 5202625 (1993-04-01), Farwell
patent: 5473617 (1995-12-01), Farwell
patent: 5490151 (1996-02-01), Feger et al.
patent: 5642364 (1997-06-01), Farwell
patent: 5668482 (1997-09-01), Roskell
patent: 5736849 (1998-04-01), Terayma

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