Boundary scan cell circuit and boundary scan test circuit

Details Boundary scan cell circuit and boundary scan test circuit Boundary scan cell circuit and boundary scan test circuit

1993-11-19

1995-09-12

Voeltz, Emanuel T.

Excavating

371 221, 371 225, 371 226, 371 27, H04B 1700

Patent

active

054504155

ABSTRACT:
The invention discloses a boundary scan cell circuit for use in checking a wire, establishing a connection between the output pin of one IC and the input pin of the other IC, for stuck-at "0"/"1" faults. In an input boundary scan cell circuit in connection with the input pin, a third selector, in response to a control signal, selects one of a signal from a logic signal input terminal and an XOR from an arithmetic unit thereby outputting a signal thus selected. The output of the third selector is latched by a first flip-flop. The arithmetic unit performs the XOR addition of the output of the first flip-flop and the value of a logic signal from the logic signal input terminal. The result of the XOR addition is scanned-out at a scan signal output terminal. This reduces the number of shift operation cycles required for scan-out of the test result thereby shortening the time taken for testing. In an output boundary scan cell circuit, test data is automatically logic-inverted, so that no shift operation cycles necessary for scan-in of inverted test data are required. Therefore, this reduces the time taken for testing.

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E. M. Rudnick et al., "An Observability Enhancement Approach for Improved Testability and AT-Speed Test", IEEE Transactions on CAD of Integrated Circuits and Systems, vol. 13, No. 8, Aug. 1994.

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