Boundary scan cell

Details Boundary scan cell Boundary scan cell

1993-07-26

1996-02-06

Canney, Vincent P.

Excavating

G01R 3128

Patent

active

054901510

ABSTRACT:
A Boundary-Scan cell (12') for facilitating testing of an electronic device (10), includes a system flip-flop (30') interposed between an output buffer (18) of the device and an internal logic block (14) which drives the buffer. The system flip-flop has asynchronous clear and preset capability which allows the flip-flop to be cleared or preset as necessary so that its output bit reflects a bit previously latched in the Boundary-Scan cell during testing. During non-testing intervals, the preset and clear capability of the system flip-flop (30') is disabled to allow the flip-flop to pass a bit between the internal logic of the device and the output buffer without undue propagation delays.

REFERENCES:
patent: 5084874 (1992-01-01), Whetsel, Jr.
patent: 5155732 (1992-10-01), Jarwala et al.
patent: 5349587 (1994-09-01), Nadeau-Dostie et al.
IEEE Standard Test Access Port and Boundary-Scan Architecture, IEEE Std. 1149.1-1990, Ch 1, "Introduction," pp. 1-1-1.5, and Ch 10, The Boundary-Scan Register, pp. 10-1-10.28.

Affiliated with

Also associated with

Rating

Boundary scan cell does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Boundary scan cell, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Boundary scan cell will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-2180479