Boundary-scan bypass circuit for integrated circuit electronic c

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G01R 3128

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056152175

ABSTRACT:
A method and apparatus for bypassing a boundary-scan cell during functional operation of an electronic component provides a component output signal (such as a data signal) to a boundary-scan bypass circuit during normal functional operation of the electronic component. The component output signal is multiplexed in the bypass circuit with the test result signal that occurs during boundary-scan testing. During functional operation of the electronic component, the component output signal is selected and provided to an output latch that is clocked by a transition of the clock signal of the electronic component. By bypassing the component output signal around the boundary-scan cell during normal operation, the traversing of the multiplexer by the component output signal after the transition of the clock signal of the component is avoided, thereby reducing off-chip delay.

REFERENCES:
patent: 5109190 (1992-04-01), Sakashita et al.
patent: 5387862 (1995-02-01), Parker et al.
patent: 5428624 (1995-06-01), Blair et al.
patent: 5448575 (1995-09-01), Hashizume
patent: 5450415 (1995-09-01), Kamada
IEEE Std 1149.1-1990, IEEE Standard Test Access Port and Boundary-Scan Architecture, Institute of Electrical and Electronics Engineers, Inc., (May 21, 1990), Chapter 1, pp. 1-1 to 1-5.

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