Boundary-scan-based system and method for test and diagnosis

Details Boundary-scan-based system and method for test and diagnosis Boundary-scan-based system and method for test and diagnosis

1993-08-30

1995-08-22

Ramirez, Ellis B.

Excavating

G01R 3128

Patent

active

054447160

ABSTRACT:
A system (10) for testing one or more circuit boards (12.sub.1 -12.sub.n), each containing at least one chain of Boundary-Scan cells (14.sub.1 -14.sub.p), includes a system test and diagnosis host (16) for managing overall testing of the system formed by the circuit boards. A Boundary-Scan Virtual Machine (BVM) (17) is operative to receive an initiate test command from the system test and diagnosis host independent of the number and nature of the boards to be tested. In response to the test command, the BVM (17) causes each circuit board to execute a test program (23) specific thereto to determine the errors, if any, in the board. The errors from each board are passed back to the BVM (17) which, in turn, interprets the errors to yield test information, indicative of the operation of the boards, which is then passed back to the system test and diagnosis host (16).

REFERENCES:
patent: 4872125 (1989-10-01), Catlin
patent: 4872169 (1989-10-01), Whotsol, Jr.
patent: 5029166 (1991-07-01), Jarwala et al.
patent: 5132635 (1992-07-01), Kennedy
IEEE Standard Test Access Port and Boundary-Scan Architecture, IEEE Std. 1149.1, IEEE Computer Society, May 1990.
C. W. Yau and N. Jarwala, "The Boundary-Scan Master: Target Applications and Functional Requirements, " Proceedings, IEEE International Test Conference, 1990 pp. 311-315.
N. Jarwala and C. W. yau, "The Boundary-Scan Master: Architecture and Implementation," Proceedings, European Test Conference 1991, pp. 1-10.
J. C. Lien and M. A. Breuer, "Test Program Systhesis for Modules and Chips having Boundary Scan,"Journal of Electronic Testing , vol. 4, No. 2, May 1993, pp. 159-180.
N. T. Jarwala and C. W. Yau, "A Structured Approach to Board-Level BIST Using the Boundary-Scan Master," Microprocessors and Microsystems, vol. 17, No. 5, Jun. 1993, pp. 289-297.
N. Jarwala and C. W. Yau, "Achieving Board-Level BIST Using the Boundary-Scan Master,"Proceedings, IEEE InternationalTest Conference, 1991, pp. 649-658.

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