Boundary independent bit decode for a SDRAM

Details Boundary independent bit decode for a SDRAM Boundary independent bit decode for a SDRAM

1995-12-14

1997-09-02

Nelms, David C.

Static information storage and retrieval

Addressing

Plural blocks or banks

36523006, 365236, G11C 800

Patent

active

056639244

ABSTRACT:
A boundary independent decoder for a Synchronous Dynamic Random Access Memory (SDRAM) with an n bit burst transfer block length. A user, usually a processor or microprocessor requests access to a block of SDRAM memory. The requested block may begin between array decode boundaries. A column address is decoded by an SDRAM column decoder. The decoder selects a starting boundary for 2n bits. The first requested bit is in the first n bits of the 2n selected bits. Thus, the entire n bit block is included in the selected 2n bit block. The n bit block is selected from the selected 2n bits and latched in a high speed decoder/register in a sequentially scrambled order, i.e., the i.sup.th bit is the first requested bit and the requested bit order is i, . . . , (n-1), . . . , 0, . . . , (i-1). Latched data is scrambled either sequentially or interleaved, if required. Scrambled data is burst transferred off chip.

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