Bottom side C4 bumps for integrated circuits

Details Bottom side C4 bumps for integrated circuits Bottom side C4 bumps for integrated circuits

1999-06-28

2001-06-19

Karlsen, Ernest (Department: 2858)

Electricity: measuring and testing

Fault detecting in electric circuits and of electric components

Of individual circuit component or element

C257S777000, C438S017000, C324S754120

Reexamination Certificate

active

06249136

ABSTRACT:

FIELD OF THE INVENTION
The present invention generally relates to integrated circuits and more particularly relates to a system and method of forming a test configuration that facilitates the use of beam probing tools in conjunction with C4 or flip-chip type device interconnection schemes.
BACKGROUND OF THE INVENTION
In the field of microelectronics, multiple integrated circuit chips are often electrically interconnected in order to achieve a desired system circuit configuration. Such interconnections typically are achieved using a conventional printed circuit board in which each integrated circuit is individually packaged, for example, in dual in-line packages (DIP) or surface mount packages. In many circuit applications, such conventional packaging and interconnection methodologies work well, however, as complex circuit systems require higher performance in terms of speed, such conventional methods have shortcomings.
One disadvantage of conventional integrated circuit packages is illustrated in prior art
FIG. 1
, designated at reference numeral
10
. The package
10
includes an integrated circuit chip
12
having a top surface
14
upon which active circuitry
16
and bond pads
18
are formed. The chip
12
is placed upon a mounting portion of a lead frame (not shown) and typically either solder-mounted or epoxy-mounted thereon. The chip
12
is electrically connected to a plurality of leads
20
(which are the lead frame pins which mount to the circuit board) via lead wires
22
. Because the lead wires
22
must not exceed predetermined lengths to avoid “collapsed loops” and since lead wires
22
should not cross one another for reliability purposes, the location of the various bond pads
18
is limited, which in some cases results in an inefficient layout of the active circuitry
16
to accommodate the bond pad locations.
In addition, the lead wires
22
are typically connected to the bond pads
18
and the lead wires
22
using a ball-bonding technique in which pressure is applied to the bond pads
18
when forming the electrical connection. In some cases, such pressure can lead to stresses in the circuitry which may compromise the circuit reliability; thus the active circuitry
16
is often not formed under the bond pads
18
as illustrated in
FIG. 1
, thus further reducing the efficiency of the circuit layout. Further, the lead wires
22
undesirably provide a resistive path between the bond pads
18
and the leads
20
which result in a small, variable voltage drops across the wires
22
and concurrent IR type heating. More significantly, the lead wires
22
have an inductance associated therewith which degrades the circuit performance of the active circuitry
16
, particularly as the performance speed of the circuitry is increased.
Another disadvantage of traditional circuit packaging methodologies is illustrated in prior art FIG.
2
. In
FIG. 2
, a portion of a circuit board substrate
30
has two integrated circuit packages
32
and
34
mounted thereon. Selective pins
36
of the packages are interconnected using printed conductive lines
38
, for example, as shown. Note that due to the circuit configuration, the conductive lines
38
are not of an equal length. At low circuit speeds, such length variations are not important, however, in certain high circuit applications, such variation in the lengths of the conductive lines
38
result in a timing skew between various control signals which must be taken into account. One method of addressing such timing skew is to make all the conductive lines
38
between the chips
32
and
34
the same length, which necessarily results in an increase in the length of some of the lines and complicates the layout of the board
30
. Alternatively, timing skew is addressed by employing synchronization circuits at the input of the various circuits and the chips
32
and
34
. Such a solution, however, increases the circuit complexity and hinders circuit performance. Clearly then, there has been a need to improve the prior art circuit packaging and interconnection methodologies for high performance circuit systems.
One solution which was developed to address the above limitations in the prior art is the use of solder bumps in a controlled, collapse chip connection (C4) structure (also often called solder bump or flip-chip bonding), as illustrated in prior art
FIG. 3
a
at reference numeral
40
. The C4 structure
40
includes a base substrate
42
, for example, a circuit socket having bond pads
44
located thereon. Solder bumps
46
are then placed on the bond pads
50
of a second (or top) substrate
48
which is oriented face-down (ie., flip-chip), aligned and brought into contact with the bond pads
44
. Electrical interconnections between the bond pads
44
and
50
are formed by heating the solder bumps
46
to a reflow temperature, at which point the solder flows; subsequent cooling results in a fixed, electrically conductive joint to be formed between the bond pads
44
and
50
.
The base substrate
42
may be a circuit socket, or alternatively may constitute an integrated circuit board. In the case of a circuit socket, a female-type socket
49
a
interfaces with an integrated circuit board
49
b,
as illustrated in prior art
FIG. 3
b.
If, however, the base substrate
42
itself is the circuit board, such C4 connection structures can be implemented on both the top surface and bottom surface thereof, as illustrated in prior art FIG.
4
. In such instances, a second semiconductor substrate
52
may similarly be oriented face-down with respect to the base substrate
42
and coupled thereto using solder bumps
46
.
The C4 structure of prior art
FIGS. 3
a
and
3
b
overcome several disadvantages of the connection methodologies of prior art
FIGS. 1 and 2
. Initially, C4 bonding eliminates the lead wires
22
and their associated resistance and inductance. Furthermore, eliminating the lead wires
22
increases the freedom a designer has to lay out the circuitry on the chip more efficiently. In addition, C4 bonding greatly reduces the conductive interconnection paths between the respective circuits, thus improving the speed and reducing the timing skew therebetween. Lastly, because the ball-bonding attachment technique is avoided, significantly less stress is placed on the bond pads during connection, which allows active circuitry to be formed under the pads. This additional level of flexibility allows the circuitry to be laid out without regard to the bond pad locations and further allows the bond pad locations above the active circuitry to be located in an optimized fashion to directly couple with circuitry on another substrate. Therefore the bond pads
50
may be located anywhere on the substrate
48
as illustrated in prior art
FIG. 5
, without the need to form such interconnections on peripheral edges of the die.
The C4 or flip-chip bonding technique discussed above does provide advantages over other prior art packaging and connection methodologies, however, the C4 connection structure does have an number of disadvantages. Typically, C4 connections are used with complex integrated circuits such as microprocessors. With such complex circuit designs, it is important to verify the design. Such design verification is performed with software via design simulations and also with hardware, by subjecting the circuit to direct testing after being fabricated.
Direct testing of the circuit may be performed in a variety of ways. One form of direct testing is called electron beam probing (i.e., e-beam) which provides the ability to evaluate electrical potentials on the die surface providing an electrical contact thereto. The electron beam probes any visible metal line of the active circuitry and the impact of the high energy electrons of the electron beam results in the emission of secondary electrons from the die surface. The secondary electrons are detected and variations in the energy of the emitted secondary electrons are monitored. Such energy variations are proportional to the surface potential of the circuitry and therefo

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