Bottom lead semiconductor chip package

Details Bottom lead semiconductor chip package Bottom lead semiconductor chip package

1998-02-13

2000-03-28

Kincaid, Kristine

Electricity: conductors and insulators

Boxes and housings

Hermetic sealed envelope type

257672, 257673, 257686, 257693, H01L 2302

Patent

active

060434309

ABSTRACT:
A bottom lead package is capable of increasing a memory capacity for a mounting position on a mother board by stacking several semiconductor packages such that exposed surfaces of leads on upper and lower surfaces of the package are aligned. The package includes a semiconductor chip, a plurality of lower leads attached to the lower side of the chip by an adhesive, a plurality of upper leads attached to the upper side of the chip by an adhesive and to the upper surfaces of the lower leads, wherein metal wires electrically connect the upper leads with a plurality of chip pads formed on the chip, and wherein a molding section packages the chip, the metal wires and the upper and lower leads, such that the upper and lower surfaces of the upper and lower leads, respectively, are externally exposed.

REFERENCES:
patent: 5363279 (1994-11-01), Cha
patent: 5583375 (1996-12-01), Tsubosaki et al.
patent: 5744827 (1998-04-01), Jeong et al.
patent: 5770888 (1998-06-01), Song et al.
patent: 5801439 (1998-09-01), Fujisawa et al.
patent: 5804874 (1998-09-01), An et al.

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