Borderless vias

Details Borderless vias Borderless vias

1997-12-18

1999-07-20

Saadat, Mahshid

Active solid-state devices (e.g., transistors, solid-state diode

Combined with electrical contact or lead

Of specified material other than unalloyed aluminum

257758, H01L 2348, H01L 2352, H01L 2940

Patent

active

059259329

ABSTRACT:
Borderless vias are formed by depositing a hard dielectric mask layer on the upper surface of a lower metal feature and forming sidewall spacers on the side surfaces of the metal feature and mask layer. A dielectric interlayer is deposited and a misaligned through-hole formed therein by etching. The dielectric material of the sidewall spacer and dielectric material of the dielectric interlayer are different. The etchant employed to form the through-hole exhibits a high selectivity with respect to the sidewall spacer material. The dielectric mask layer enables the formation of a sidewall spacer extending above the metal feature such that, after etching to form the misaligned through-hole, the sidewall spacer covers the side surface of the metal feature.

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