Bootstrapping level control circuit for word line signal produci

Electrical transmission or interconnection systems – Nonlinear reactor systems – Parametrons

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307443, 307465, 307553, 36523006, 36518909, 36518911, H03K 1912, H03K 19096

Patent

active

050737317

ABSTRACT:
A bootstrapping level control circuit for use in a word line signal producing circuit in a DRAM is disclosed. The bootstrapping level control circuit detects an existing potential level at a word line signal source and provides variable bootstrapping efficiency according to the detected existing potential level at the word line signal source to supply sufficient supply voltage Vcc of the word line signal source to a memory cell array apparatus and to thereby prevent double bootstrapping effects from occurring in a word line signal transferring control circuit. The bootstrapping level control circuit further comprises a Vcc level detector for detecting the existing potential level at the word line signal source. The Vcc level detector includes a first, second and a third Vcc level detecting circuits with each Vcc level detecting circuit having a predetermined inverting level, respectively, being different relative to each other. A logic combination circuit is provided for logically combining a bootstrapping control signal with each detected signal detected by each first, second and third Vcc level detecting circuit. An inverting circuit is also provided for delaying each logically combined signal from the logic combination circuit to invert each logically combined signal. A bootstrapping circuit is provided for bootstrapping a bootstrapping point by receiving each inverted signal, such that, in use, the bootstrapping point is bootstrapped depending upon the inverted signals from the inverting circuit, thereby varying bootstrapping efficiency of the bootstrapping level control circuit depending upon the potential level detected at the word line signal source.

REFERENCES:
patent: 4896297 (1990-01-01), Miyatake et al.
patent: 4922138 (1990-05-01), Hashimoto et al.
IBM Tech. Disc. Bul., "Dynamic Logic Driver", Long et al., vol. 17, No. 7, 12/74.

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