Miscellaneous active electrical nonlinear devices – circuits – and – Specific identifiable device – circuit – or system – With bootstrap circuit
Reexamination Certificate
2002-07-26
2003-10-21
Lam, Tuan T. (Department: 2816)
Miscellaneous active electrical nonlinear devices, circuits, and
Specific identifiable device, circuit, or system
With bootstrap circuit
C327S307000, C330S261000, C330S269000
Reexamination Certificate
active
06636111
ABSTRACT:
BACKGROUND OF THE INVENTION
A differential amplifier is a well-known circuit containing two inputs in which the output is proportional to the instantaneous differences between the two input signals. An ideal differential amplifier is designed to amplify the differences between the two input voltages while rejecting any signal elements they have in common. The amount of voltage common to both input lines of the differential amplifier is referred to as the common-mode voltage. The remainder is referred to as the differential voltage.
The common-mode voltage generally generates a common-mode base current which includes alternating current (ac) and direct current (dc) components. The dc component is referred to as the input bias current of the differential amplifier. The input bias current is undesirable and there are several prior art techniques to cancel as big a portion of it as possible.
FIG. 1
schematically illustrates a prior art scheme for input bias current cancellation of input transistors of a differential amplifier. An arrangement
100
is shown which includes positive and negative supply rails
110
and
120
respectively, NPN transistors Q
1
, Q
2
, Q
3
, Q
4
, Q
5
, Q
6
, Q
10
and Q
11
, PNP transistors Q
7
, Q
8
, Q
9
, Q
12
and Q
13
, and current sources IS
1
130
and IS
2
140
. The transistors Q
1
and Q
2
form the input stage of the differential amplifier
150
. It is understood that in one embodiment, the input stage includes two PNP transistors. In such an embodiment, the transistors Q
1
, Q
2
, Q
3
, Q
4
, Q
5
, Q
6
, Q
10
and Q
11
include PNP transistors and the transistors Q
7
, Q
8
, Q
9
, Q
12
and Q
13
include NPN transistors.
In this description, the NPN and PNP transistors function in a manner that will be apparent to those of ordinary skill in the art. For this reason and to keep the description focused on the essence of the present invention, the design and operation of the individual transistors of the arrangement
100
are not mentioned in great detail. The NPN and PNP transistors are also referred to as the first and second conductivity type transistors respectively, or vice versa. Furthermore, the NPN and PNP transistors are also referred to as one conductivity type and opposite conductivity type transistors respectively, or vice versa.
Also, the terms rail, current source, tail current, input stage, PNP input stage, NPN input stage, base, emitter, collector, diode-connected transistor, bootstrap circuit and area of a transistor are used according to their ordinary meanings. Also, the term couple is used in its ordinary generally understood sense to mean to join two circuits, enabling signals to be transferred from one to another. The two circuits can be directly connected to each other or through an intervening element such as a third circuit. Also, the term electronic load is used in its ordinary generally understood sense to mean one or more resistors, one or more transistors, a current source coupled to one or more transistors, a current source coupled to one or more resistors, or a current source coupled to one or more resistors and one or more transistors. Finally, the terms sense and track are used in their ordinary generally understood sense to mean to detect current and to mimic the detected current respectively.
The arrangement
100
is used to cancel the input bias currents of the transistors Q
1
and Q
2
. The transistors Q
3
and Q
4
are coupled to the transistors Q
1
and Q
2
respectively such that the base current of Q
3
tracks the input bias current of Q
1
and the base current of Q
4
tracks the input bias current of Q
2
. The collector-emitter voltages (VCE) of the transistors Q
1
, Q
2
, Q
3
and Q
4
are the same and constant over the common mode range. Lateral transistors Q
7
and Q
8
are connected to the bases of the tracking transistors Q
3
and Q
4
respectively to current-mirror the base currents of Q
3
and Q
4
. The mirrored currents are injected into the bases of the input transistors Q
1
and Q
2
to effectively cancel the input bias currents of these transistors Q
1
and Q
2
.
The arrangement
100
can be referred to as a bootstrap circuit because the transistors Q
9
, Q
10
and Q
11
form a bootstrap loop
160
. The bootstrap loop
160
is connected to the emitters of the transistors Q
1
, Q
2
, Q
7
and Q
8
and the bases of the transistors Q
5
and Q
6
such that the cancellation currents in the emitters of the transistors Q
7
and Q
8
will track the input bias currents of the transistors Q
1
and Q
2
when the common-mode input voltages fluctuate. The transistors Q
10
and Q
11
are diode-connected transistors.
The current source IS
1
130
ensures that the current flowing from the emitters of the transistors Q
1
and Q
2
into the current sink (negative rail)
120
is always constant.
The current source IS
2
140
ensures that the current in the loop
170
formed by the transistors Q
9
, Q
10
, Q
11
, Q
12
and Q
13
is always constant. The IS
2
140
current is mirrored to the transistor Q
12
through the diode-connected transistor Q
13
. The collector current of the transistor Q
12
is used to bias the bootstrap loop
160
.
A disadvantage of the above circuit
100
is that the voltage drops caused by the transistors Q
12
, Q
8
, Q
4
and Q
2
limit the common-mode input voltage range over which the input bias currents are cancelled to being about 1.1 VDC away from the positive supply rail
110
. In another words, the above arrangement
100
does not support input bias current cancellation for rail-to-rail differential amplifiers. The following numerical example illustrates the point.
In this example, the positive supply rail
110
voltage is +5 VDC and the negative supply rail
120
voltage is 0 VDC, the current gains (&bgr;) of the NPN transistors Q
1
and Q
2
are 100, the input bias current before cancellation is 1 micro ampere (&mgr;A), and the diode voltage drops across the active and saturated transistors are 0.7 VDC and 0.2 VDC respectively. For circuit analysis of the arrangement
100
, the transistors Q
2
and Q
12
are saturated and the transistors Q
4
and Q
8
are active.
A circuit analysis of the arrangement
100
provides the IS
1
130
current at 202 &mgr;A, the voltages of 4.8 VDC and 4.1 VDC at the transistor Q
8
emitter and base respectively, 3.4 VDC at the transistor Q
4
emitter, 3.2 VDC at the transistor Q
2
emitter and 3.9 VDC at the common-mode input. The common-mode input voltage range over which the input bias currents are cancelled is limited to being about 1.1 VDC away from the positive supply rail
110
.
It is understood that in a similar example in which the differential amplifier
150
includes a PNP transistors input stage, the common-mode input voltage range over which the input bias currents are cancelled is limited to being about 1.1 VDC away from the negative supply rail. For such an example, the transistors Q
1
, Q
2
, Q
3
, Q
4
, Q
5
, Q
6
, Q
10
and Q
11
are PNP transistors and the transistors Q
7
, Q
8
, Q
9
, Q
12
and Q
13
are NPN transistors. Also, for such an example, the supply rail
110
is a negative supply rail and the supply rail
120
is a positive supply rail.
SUMMARY OF THE INVENTION
The present invention discloses a circuit to cancel an input bias current of a differential amplifier. In one embodiment, the circuit (
200
) includes an input stage (
210
) of the differential amplifier including first and second PNP transistors (Q
21
and Q
22
). The collector of the first PNP transistor (Q
21
) is coupled to a first resistor (
240
), the collector of the second PNP transistor (Q
22
) is coupled to a second resistor (
250
), and the first and second resistors (
210
and
250
) are coupled to a negative supply rail. (
230
)
A tail current circuit (
272
) coupled to a positive supply rail (
220
) and the emitters of the first and second PNP transistors (Q
21
and Q
22
) is disclosed. Also, a compensating current circuit (Q
24
) coupled to the tail current circuit (
272
) and the positive supply rail (
220
) is disclosed.
A third PNP transistor (Q
Gross William H.
Tran Danh T.
Fish & Neave
Joshi Vinay V.
Lam Tuan T.
Linear Technology Corporation
Rowland Mark D.
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