Bootstrap circuit for word line driver in semiconductor memory

Details Bootstrap circuit for word line driver in semiconductor memory Bootstrap circuit for word line driver in semiconductor memory

1991-06-12

1992-10-06

Hudspeth, David

Electrical transmission or interconnection systems

Nonlinear reactor systems

Parametrons

307451, 307246, 36518909, H03K 1704

Patent

active

051534673

ABSTRACT:
In a driver circuit for word lines of a semiconductor memory, a CMOS inverter stage and a first FET are connected to opposite terminals of a capacitor to alternately connect the capacitor across the terminals of the power supply for charging the capacitor and between the power supply and the load to add the voltages of the power supply and the capacitor. Second and third FETs form a latch that has one output connected to control the inverter stage and the other output connected to control the first FET. Fourth and fifth FETs are connected to receive a timing signal and to produce true and complement phases for controlling the latch.

REFERENCES:
patent: 4471240 (1984-09-01), Novosel
patent: 4484092 (1984-11-01), Campbell, Jr.
patent: 4494018 (1985-01-01), Clemen et al.
patent: 4697111 (1987-09-01), Van Zantan et al.
patent: 4922128 (1990-05-01), Dhong et al.
patent: 4922138 (1990-05-01), Hashimoto et al.
patent: 4954731 (1990-09-01), Dhong et al.
patent: 5038325 (1991-08-01), Douglas et al.

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