Bootstrap circuit

Details Bootstrap circuit Bootstrap circuit

2001-12-27

2003-05-06

Zweizig, Jeffrey (Department: 2816)

Miscellaneous active electrical nonlinear devices, circuits, and

Gating

Signal transmission integrity or spurious noise override

Reexamination Certificate

active

06559707

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The invention relates generally to a bootstrap circuit, and more particularly to, a word line bootstrap circuit for implementing a high-speed flash memory and a memory cell having a good data holding capability.
2. Description of the Prior Art
Generally, in order to increase the speed of a read operation in a flash memory cell driven with a low voltage upon a read operation, a low potential supply voltage (LOW Vcc; LVcc) is bootstrapped using a bootstrap circuit to supply the bootstrapped voltage to a word line.
In case that the bootstrap circuit is used to boost the word line voltage, there is a problem of a retention since it is difficult to exactly read the cell current if the word line voltage boosted by the bootstrap circuit is too low and stress is applied to the cell gate if the word line voltage is too high. Therefore, the word line voltage boosted by the bootstrap circuit must be boosted within a given range of voltage.
Referring now to
FIG. 1
, a construction of a conventional word line bootstrap circuit will be below explained.
The conventional word line bootstrap circuit includes a first stage
10
~third stage
30
for pumping the supply voltage ‘Vcc’ applied to the word line over three steps.
The first stage
10
includes a first precharging unit
11
for precharging a first node Q
1
with a given potential ‘Vcc’ or ‘Vcc−Vt’ depending on a first clock signal CLK
1
, and a first capacitor C
1
for pumping the first node Q
1
with a first potential ‘V
1
’ depending on a kick signal KICK.
The second stage
20
includes a second precharging unit
21
for precharging a second node Q
2
with a given potential ‘Vcc’ or ‘Vcc−Vt’ depending on the first clock signal CLK
1
, a first PMOS transistor P
1
connected between the first node Q
1
and the third node Q
3
and driven by a second clock signal CLK
2
, a first NMOS transistor N
1
connected between the third node Q
3
and the ground Vss and driven by a third clock signal CLK
3
, and a second capacitor C
2
connected between the second node Q
2
and the third node Q
3
, for pumping the second node Q
2
with a second potential ‘V
2
’.
The third stage
30
includes a third precharging unit
31
for precharging a fourth node Q
4
with a given potential ‘Vcc’ or ‘Vcc−Vt’ depending on the first clock signal CLK
1
, a second PMOS transistor P
2
connected between the second node Q
2
and the fifth node Q
5
and driven by the second clock signal CLK
2
, a second NMOS transistor N
2
connected between a fifth node Q
5
and the ground Vss and driven by the third clock signal CLK
3
, and a third capacitor C
3
connected between the fourth node Q
4
and the fifth node Q
5
, for pumping the fourth node Q
4
with the third potential ‘V
3
’.
A method of driving the conventional word line bootstrap circuit constructed as above will be below described by reference to
FIG. 2
showing a waveform of each of signal inputted respective stages.
Referring now to
FIG. 2
, during period from a first time T
0
to a second time T
1
, the first, the second and third clock signals CLK
1
, CLK
2
and CLK
3
are kept at a LOW state and the kick signal KICK are kept to be at HIGH state.
In this state, at the second time T
1
, if the first, second and third clock signals CLK
1
, CLK
2
and CLK
3
are shifted from a LOW state to a HIHG state and the kick signal KICK is shifted from a HIGH state to a LOW state, in a positive edge period where the state is changed to a HIGH state, the first, the second and third pre-charging units
11
,
21
and
31
are driven by the first clock signal CLK
1
, the first and second PMOS transistors P
1
and P
2
are turned off by the second clock signal CLK
2
and the first and second NMOS transistors N
1
and N
2
are turned on by the third clock signal CLK
3
.
Therefore, a current path is formed between the first precharging unit
11
and a source of the kick signal KICK to pre-charge the first pre-charging unit
11
with the supply voltage ‘Vcc’ outputted from the first capacitor C
1
, so that the first node Q
1
is precharged with the potential of the supply voltage ‘Vcc’. Also, a current path is formed between the second precharging unit
21
and the ground Vss through the first NMOS transistor N
1
to precharge the second capacitor C
2
with the supply voltage ‘Vcc’ outputted from the second precharging unit
21
, so that the second node Q
2
is precharged with the potential of the supply voltage ‘Vcc’. Also, a current path is formed between the third precharging unit
31
and the ground Vss through the second NMOS transistor N
2
to precharge the third capacitor C
3
with the supply voltage ‘Vcc’ outputted from the third precharging unit
31
, so that the fourth node Q
4
is precharged with the potential of the supply voltage ‘Vcc’.
In a period from the second time T
1
to a third time T
2
, the first, the second and the third clock signals CLK
1
, CLK
2
and CLK
3
are kept at a HIGH state the kick signal KICK is kept at a LOW state. Thus, the potential of the first node Q
1
, the second node Q
2
and the fourth node Q
4
maintain the potential of the supply voltage ‘Vcc’.
In this state, at third time T
2
, if the first, the second and third clock signals CLK
1
, CLK
2
and CLK
3
are shifted from a HIGH state to a LOW state and the kick signal KICK is shifted from a LOW state to a HIGH state, in a negative edge period where the state is changed to a LOW state, the first, the second and the third pre-charging units
11
,
21
and
31
are not driven by the first clock signal CLK
1
, the first and second PMOS transistors P
1
and P
2
are turned on by the second clock signal CLK
2
, and the first and second NMOS transistors N
1
and N
2
are turned off by the third clock signal CLK
3
.
Therefore, the first potential ‘V
1
’ on the first node Q
1
is increased by a potential corresponding to the kick signal KICK. For example, if the potential of the kick signal KICK is ‘Vcc’ same to the supply voltage ‘Vcc’, the first potential ‘V
1
’ is increased by ‘2Vcc’. Then, the second potential ‘V
2
’ on the second node Q
2
is increased by ‘3Vcc’ since the first potential ‘V
1
’ is transmitted through the first PMOS transistor P
1
that was turned on by the second clock signal CLK
2
. Also, the third potential ‘V
3
’ on the fourth node Q
4
is increased by ‘4Vcc’ since the second potential V
2
is transmitted through the second PMOS transistor P
2
that was turned on by the second clock signal CLK
2
. Therefore, a boosting voltage Vboot outputted to an output terminal of a final word line bootstrap circuit is increased by ‘4Vcc’.
As described above, the boosting voltage Vboot outputted to the output terminal of the conventional word line bootstrap circuit can be represented by a following Equation 1.
V
boot=&agr;
V
2
+
Vcc
=&agr;(&agr;
V
1
+Vcc
)+
Vcc
=&agr;{&agr;(&agr;
Vcc+Vcc
)+
Vcc}+Vcc
=&agr;{&agr;
2
Vcc+&agr;Vcc+Vcc}+Vcc
=&agr;
3
Vcc
+&agr;
2
Vcc+&agr;Vcc+Vcc
=(&agr;
3
+&agr;
2
+&agr;+1)
Vcc
  [Equation 1]
where ‘&agr;’ is the coupling ratio of capacitors in respective stages.
If the coupling ratio ‘&agr;’ of capacitors constituting respective stages is “1”, the boosting voltage Vboot is
4
Vcc according to Equation 1. At this time, what the coupling ratio ‘&agr;’ is “1” means that the capacitor transmits 100% boosting voltage Vboot. Generally, the coupling ratio ‘&agr;’ of a capacitor is about 0.6~0.7(60~70%).
In other words, as represented in Equation 1, a problem in the conventional word line bootstrap circuit is that if the coupling ratio ‘&agr;’ of the capacitor is determined, the boosting voltage Vboot is changed in proportion to Vcc. For example, in a Vcc operation of 1.6~2V, the sum of the coupling ratio ‘&agr;’ of a capacitor constituting all the stages is “3” (i.e., (&agr;
3
+&agr;
2
+&agr;+1)=3)), the voltage range of the boosting voltage Vboot is increased to

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