Booth's multiplier

Details Booth's multiplier Booth's multiplier

1987-03-06

1989-02-21

Harkcom, Gary V.

Boots, shoes, and leggings

G06F 752

Patent

active

048071757

ABSTRACT:
In Booth's method of calculating a product of a multiplicand X and a multiplier Y, Y is divided into plural partial multipliers PP.sub.i (Y.sub.i, Y.sub.i+1, Y.sub.i+2); partial products PD.sub.i are formed separately in sequence by multiplying X by each of decoded partial multiplier values V.sub.pp decoded in accordance with Booth theory; and all the partial products PD.sub.i are accumulatively added to obtain the product. To increase the processing speed twice in spite of a relatively simple circuit configuration, two partial products of X and V.sub.pp are formed simultaneously in sequence and added to obtain a partial product sum PS.sub.i, and all the two partial product sums are accumulatively added to obtain a final result.

REFERENCES:
patent: 4153938 (1979-05-01), Ghest et al.
patent: 4168530 (1979-09-01), Gajski et al.
patent: 4546446 (1985-10-01), Machida
patent: 4575812 (1986-03-01), Kloker et al.
IBM Technical Disclosure Bulletin, vol. 27, No. 11, Apr. 1985, "Improved Approach to the Use of Booth's Multiplication Algorithm", pp. 6624-6632.
Beraud et al. "Parallel Multiplier", IBM Tech. Disclosure Bulletin, vol. 24, No. 11B, 4/82, pp. 6090-6092.
Waser et al, "Real-Time Processing Gains Ground with Fast Digital Multiplier", Electronics, Sep. 29, 1977, pp. 93-99.
Nikkei Electronics-May 29, 1978 by Z. Tanaka, pp. 76-90.
Computer High-Speed Calculations "KINDAI KAGAKU" by Horikoshi-Sep. 1, 1981, pp. 152-157.

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