Booth's conversion circuit

Details Booth's conversion circuit Booth's conversion circuit

1987-05-13

1989-01-17

Heyman, John S.

Electrical transmission or interconnection systems

Nonlinear reactor systems

Parametrons

307243, 307452, H03K 1921, H03K 19094, H03K 19017

Patent

active

047989807

ABSTRACT:
A Booth's algorithm conversion circuit having first and second switches controlled by input signals QX and Q2X and receiving as input, signals X.sub.i of a logic level positioned in the i digit order of a multiplicand X and signal X.sub.i-1 of a logic level positioned in the i-1 digit order of multiplicand X. The outputs of the first and second switches are tied together and to ground via first and second transitors controlled by signals QX and Q2X, the first and second transistors conducting in an inverse relationship to the first and second switch circuits. The common output of the first and second switch circuits is input to an exclusive OR circuit which receives an additional logic 1 or logic 0 input signal to produce the Booth's converted output. The resulting number of circuit elements and gates provides a simplified, high speed and small circuit for producing the Booth's conversion.

REFERENCES:
patent: 4238833 (1980-12-01), Ghest et al.
patent: 4570085 (1986-02-01), Redfield
patent: 4595845 (1986-06-01), Briggs
patent: 4649290 (1987-03-01), Yamamoto
patent: 4716312 (1987-12-01), Mead et al.
"CMOS Transfer Gate Exclusive OR Circuit", IBM Tech. Discl. Bull., vol. 28, No. 10, Mar. 1986, pp. 4303-4304.
Craig, "Single-Phase Clocked CMOS Latch", IBM Tech. Discl. Bull., vol. 26, No. 8, pp. 4423-4424, Jan. 1984.

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