Booth multiplier with low power, high performance input circuitr

Details Booth multiplier with low power, high performance input circuitr Booth multiplier with low power, high performance input circuitr

1995-01-30

1998-03-31

Mai, Tan V.

Boots, shoes, and leggings

G06F 752

Patent

active

057346011

ABSTRACT:
A Booth multiplier for multiplying a first number with a second number to produce a product has an array of adder cells arranged in a plurality of rows of adder cells and is provided with input circuitry that reduces the power consumption of the multiplier. This input circuitry includes a plurality of Booth recoding logic cells that provide the control signals to multiplexers in the adder cells in the array. The Booth recoding logic cells receive different subsets of bits of the second number and generate the Booth recoded control signals as a function of the received subset of bits. Each Booth recoding logic cell includes balanced logic circuitry for generating all of the Booth recoded control signals from that Booth recoding logic cell at the same time. The balanced logic circuitry minimizes temporary short-circuit paths in the multiplexers in the adder cells. The input circuitry also includes a split bus that provides the first number to the array. The split bus has a first branch that provides the first number unbuffered to the top row of the array, and a second branch having a buffer circuit and providing the first number buffered to the other rows of the array. The buffer circuit has low-power, low-speed buffers since the top row is able to receive the first number unbuffered, and the remaining rows in the array do not need to receive the first number until after the top row of adder cells completes its addition.

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patent: 5343417 (1994-08-01), Flora
Waser; High-Speed Monolithic Multipliers for Real-Time Digital Signal Processing; IEEE 1978 pp. 19-29.

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