Booth multiplier with high speed output circuitry

Details Booth multiplier with high speed output circuitry Booth multiplier with high speed output circuitry

1995-01-30

1997-06-10

Mai, Tan V.

Boots, shoes, and leggings

G06F 752

Patent

active

056383134

ABSTRACT:
A Booth multiplier for multiplying a first number with a second number to produce a product has an array of adder cells arranged in rows and produces addition results of bits from the first and second numbers. A carry lookahead circuit is coupled to a right side of the array to receive a portion of the addition results and produce the least significant bits of the product. A total delay through the carry lookahead circuit is equal to a total delay through the array of adder cells. A pipeline latch is provided for latching the least significant bits of the product and the addition results from a bottom row of the array of adder cells. An output adder receives the latched addition results of the adder cells of the bottom row and generates the most significant bits of the product. The output adder includes a carry lookahead adder that receives a first subset of the addition results from the adder cells of the bottom row, a first carry select adder that receives a second subset of the addition results from the adder cells of the bottom row, and a second carry select adder that receives a third subset of the bottom row of the addition results from the adder cells of the bottom row. Each of the carry lookahead adder, the first carry select adder and the second carry select adder produces a different subset of the most significant bits of the product.

REFERENCES:
patent: 4573137 (1986-02-01), Ohhashi
patent: 4575812 (1986-03-01), Kloker et al.
patent: 5146421 (1992-09-01), Adiletta et al.
patent: 5343417 (1994-08-01), Flora
Waser, "High-Speed Monolithic Multipliers for Real-Time Digital Signal Processing", IEEE 1978 pp. 19-29.

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