Booth encoding circuit for a multiplier of a...

Details Booth encoding circuit for a multiplier of a... Booth encoding circuit for a multiplier of a...

2005-04-05

2005-04-05

Chaki, Kakali (Department: 2124)

Electrical computers: arithmetic processing and calculating

Electrical digital calculating computer

Particular function performed

C708S620000

Reexamination Certificate

active

06877022

ABSTRACT:
A Booth encoding circuit includes a plurality of cells (202a-202d), in which at least one of the cells (202c) includes a plurality of inputs. The cell also includes a first plurality of transistors (203) receiving at least one input and forming a NAND logic stage. The cell further includes a second plurality of transistors (211) receiving at least one input and forming an OR logic stage. The cell also includes a first output inverter (222) connected to at least one of the second plurality of transistors (211), and a first switching (224) connected to at least one of the first plurality of transistors (203). The cell further includes a second switching (226) connected to the first output inverter (222), and a second output inverter (228) connected to the first switching (224) and the second switching (226).

REFERENCES:
patent: 4718031 (1988-01-01), Nukiyama
patent: 5151875 (1992-09-01), Sato
patent: 5442576 (1995-08-01), Gergen et al.
patent: 6065032 (2000-05-01), Nicol
patent: 6125379 (2000-09-01), Lin
patent: 6535902 (2003-03-01), Goto
Kiwon et al., Design of a high performance 32×32 bit multiplier with a novel sign select Booth encoder, 2001, IEEE, pp. 701-704.*
Issam et al., Circuit techniques for CMOS low-power high-performance multipliers, 1996, IEEE Journal of solid-state circuits, vol. 31, No. 10, pp. 1535-1546.

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