Boot-strapped decoder circuit

Details Boot-strapped decoder circuit Boot-strapped decoder circuit

1990-10-02

1992-11-24

Hudspeth, David

Electrical transmission or interconnection systems

Nonlinear reactor systems

Parametrons

307443, 307482, 36523004, H03K 1704

Patent

active

051665549

ABSTRACT:
A boot-strapped decoder circuit in accordance with the present invention activates a selected word line output in response to an input address. The decoder circuit includes a plurality of row decoders, each of which has a plurality of word line outputs. The row decoders respond to a select signal that identifies one of the row decoders as a selected row decoder. The select signal is generated by a regular predecoder based on the most significant bits of the input address. Low order predecoder circuitry utilizes the least significant bits of the input address to generate a low order decoder signal. The selected row decoder includes boosting means coupled to each of the selected row decoder outputs and responsive to the low order predecode signal for generating a boot-strapped output voltage on a selected word line output of the selected row decoder.

REFERENCES:
patent: 4471240 (1984-09-01), Novosel
patent: 4622479 (1986-11-01), Taylor
patent: 4673829 (1987-06-01), Gupta
patent: 4678941 (1987-07-01), Chao et al.
patent: 4692638 (1987-09-01), Stiegler
patent: 4814647 (1989-03-01), Tran

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