Static information storage and retrieval – Floating gate – Particular connection
Reexamination Certificate
2001-05-30
2002-12-24
Nelms, David (Department: 2818)
Static information storage and retrieval
Floating gate
Particular connection
C365S185330, C365S218000
Reexamination Certificate
active
06498750
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor memory device (e.g., an IC memory card) utilizing a boot block flash memory; a boot block flash memory control circuit used for such a semiconductor memory device; and an erasure method for a boot block flash memory.
2. Description of the Related Art
Flash memories can be classified into symmetrical block flash memories and boot block flash memories. A symmetrical block memory includes “symmetrical blocks”, i.e., blocks having the same capacity. A boot block flash memory includes both symmetrical blocks and boot blocks, such that each boot block has a different capacity from that of each symmetrical block. Conventionally, a majority of flash memory-based IC memory cards, as shown in
FIG. 12A
, adopt a symmetrical block flash memory structure having symmetrical blocks of e.g., 64 kbytes. Therefore, conventional IC memory card applications often incorporate card controlling software intended for such IC memory cards of a symmetrical block flash memory type. Such card controlling software is not intended for IC memory cards of a boot block flash memory type.
Accordingly, there is a problem in that a majority of IC memory card applications on the market, whose card controlling software cannot be updated, can only utilize IC memory cards of a symmetrical block flash memory type.
Furthermore, an IC memory card of a boot block flash memory type as shown in
FIG. 12B
, may have a different boot block size (capacity) from manufacturer to manufacturer. Therefore, each IC memory card product requires a specially-designed data rewriting program. This requirement detracts from their versatility.
Hence, in order for IC memory cards to be versatile, they need to utilize symmetrical block flash memories. Thus, IC memory cards of a symmetrical block flash memory type may be versatilely used with respect to IC memory card applications which are adapted thereto; however, there still remains a problem with IC memory cards of a boot block flash memory type, in that such IC memory cards cannot be versatilely used.
Accordingly, a semiconductor memory device is proposed in Japanese Laid-Open Publication No. 6-119230, for example, in which a boot block mode and a symmetrical block mode are switchable so that either a symmetrical block flash memory portion or a boot block flash memory portion thereof can be used at a time, as shown in
FIGS. 13A and 13B
.
However, the technique disclosed in Japanese Laid-Open Publication No. 6-119230 requires both a boot block memory and a symmetrical block memory to be provided on a chip, resulting in the problem of increased chip area and hence increased cost.
On the other hand, Japanese Laid-Open Publication No. 10-241377 discloses a semiconductor memory device featuring a boot block flash memory in which the same address counter is used for designating cells in both symmetrical blocks and irregular blocks (i.e., boot blocks), thereby attempting to reduce the scale of the circuitry.
However, when performing a block erasure, the technique disclosed in Japanese Laid-Open Publication No. 10-241377 cannot change the size of the block to be erased; i.e., the boot blocks cannot be operated in the same fashion as symmetrical blocks. As a result, this boot block flash memory is not interchangeable with a symmetrical block flash memory. Another problem associated with conventional IC memory cards is that, when erasing data in a plurality of boot blocks in an IC memory card of a boot flash memory type, a host system must designate individual ones of the plurality of boot blocks, and it is necessary to issue plural instances of an erase command.
SUMMARY OF THE INVENTION
According to one aspect of the present invention, there is provided a boot block flash memory control circuit for controlling a boot block flash memory, the boot block flash memory including at least one symmetrical block each having a first capacity and a plurality of asymmetrical blocks each having a capacity smaller than the first capacity, wherein: the boot block flash memory control circuit detects a first address signal designating an address in the boot block flash memory and a first command signal for causing the boot block flash memory to operate, and based on the detected first address signal and first command signal, outputs a second command signal and a second address signal for erasing data stored in one of the at least the one symmetrical block or a subset of the plurality of asymmetrical blocks.
In one embodiment of the invention, a total capacity of the subset of asymmetrical blocks is equal to the first capacity of the at least one symmetrical block.
In another embodiment of the invention, while data stored in the subset of asymmetrical blocks is erased, a READY signal and an operation status signal, which are similar to a READY signal and an operation status signal to be output when data stored in one of the at least one symmetrical block is erased, are output.
In still another embodiment of the invention, the boot block flash memory control circuit further includes : a boot block address detection circuit for detecting a first block designating address signal which designates the subset of asymmetrical blocks and outputting a first signal based on the first block designating address signal; a command detection circuit for outputting a second signal based on the first signal, a first block erase command signal for erasing data stored in the subset of asymmetrical blocks, and a first control signal; and an address/command generation circuit for outputting the second address signal and the second command signal to the subset of asymmetrical blocks based on the second signal and a second control signal from the boot block flash memory.
In still another embodiment of the invention, the boot block flash memory control circuit further includes a READY signal/status signal control circuit for outputting a signal indicating an erasure state while the subset of asymmetrical blocks are erased.
In still another embodiment of the invention, at least one of the plurality of asymmetrical blocks includes a boot block or a parameter block.
According to another aspect of the present invention, there is provided an IC memory card including: a boot block flash memory; and an interface IC for controlling the boot block flash memory based on an external signal, wherein the interface IC includes the aforementioned boot block flash memory control circuit.
In one embodiment of the invention, in a memory space of the boot block flash memory, a plurality of asymmetrical blocks in the boot block flash memory are decoded to an address region which is substantially unlikely to be accessed.
In another embodiment of the invention, in a memory space of the boot block flash memory, a plurality of asymmetrical blocks in the boot block flash memory are decoded so as to be deleted from the memory space.
According to yet another aspect of the present invention, there is provided a semiconductor memory device including: a host system; a boot block flash memory; and a boot block flash memory control circuit for controlling the flash memory based on a signal from the host system, wherein the boot block flash memory control circuit is the aforementioned boot block flash memory control circuit.
According to yet another aspect of the present invention, there is provided a method for erasing data stored in a boot block flash memory including a plurality of asymmetrical blocks, including the steps of: outputting a first signal based on a first block designating address signal which indicates a block designating address of a subset of the plurality of asymmetrical blocks input from the host system; outputting a second signal based on the first signal, a first block erase command signal, and a first control signal; outputting a second block designating address signal and a second block erase command signal to the boot block flash memory, based on the second signal and a second control signal from the boot block flash memory; and outputt
Le Thong
Morrison & Foerster / LLP
Sharp Kabushiki Kaisha
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