Boosting word-line clock circuit for semiconductor memory

Details Boosting word-line clock circuit for semiconductor memory Boosting word-line clock circuit for semiconductor memory

1984-11-19

1987-01-27

Heyman, John S.

Electrical transmission or interconnection systems

Nonlinear reactor systems

Parametrons

307264, 307269, 307448, 307452, H03K 19096

Patent

active

046396225

ABSTRACT:
A voltage boosting circuit combination for semiconductor memory word-lines having a charge/discharge circuit including a first pair of MOSFET's and connected to a first clock signal. An output lead is connected from the charge/discharge circuit to a word-line of a semiconductor memory. The first clock signal .PHI.A thereon is connected to the charge/discharge circuit for actuating the MOSFET's to produce a voltage change on the output lead from a first voltage level to a second voltage level. The circuit combination also includes a threshold voltage circuit having a second pair of MOSFET's, which is connected to a second clock signal .PHI.C for controlling the voltage level in the threshold voltage circuit. A lead is provided connecting the threshold voltage circuit to the charge/discharge circuit. The circuit combination further includes an output signal boosting circuit having a third pair of MOSFET's which is connected to a third clock signal .PHI.D for actuating the MOSFET's to produce a voltage boosting signal. A capacitor device is provided for connecting the boosting circuit to the output lead for applying the voltage boosting signal from the voltage boosting circuit to the output lead for enhancing the voltage level change on the output lead to the first voltage level from the second voltage level.

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