Electric power conversion systems – Current conversion – With voltage multiplication means
Reexamination Certificate
2000-11-02
2002-07-02
Berhane, Adolf Deneke (Department: 2838)
Electric power conversion systems
Current conversion
With voltage multiplication means
Reexamination Certificate
active
06414862
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to boosting circuits for boosting the power-supply voltage, and particularly to a word line boosting circuit for generating a voltage in reading operation in a semiconductor storage device having semiconductor non-volatile memory elements.
2. Description of the Background Art
In these years, there is a growing trend toward use of lower power-supply voltages in semiconductor devices in order to reduce the dissipation of power or for another purpose. Also, some semiconductor devices may be required to allow for a wide range between the upper and lower limits of the power-supply voltage. Moreover, in applications of semiconductor devices to various products, the specifications of the required permissible range of the power-supply voltage may differ depending on the product type.
The use of lower, and an increasing variety of, power-supply voltage values are demanded also for semiconductor storage devices having semiconductor non-volatile memory elements such as flash memory elements. In the semiconductor non-volatile memory elements, however, simply lowering the power-supply voltage will increase the read time and thus hinder high-speed operation.
Accordingly such semiconductor storage devices require word line boosting circuits for boosting the word line voltage from the power-supply voltage in reading operation. The word line boosting circuits are required to operate only when needed, e.g. during reading operation, and to be inactive in other states, e.g. during standby state, so as not to waste power.
Now,
FIG. 29
shows an example of the configuration of a semiconductor storage device having semiconductor non-volatile memory elements. In
FIG. 29
, the semiconductor storage device has a memory cell array AR, a data input/output buffer DB for buffering data signals D
0
to Dk inputted/outputted to and from the memory cell array AR, and an address buffer AB for buffering address signals A
0
to Aj for addressing locations in the memory cell array AR. The memory cell array AR includes a plurality of cells regularly arranged therein, each memory cell including a selecting transistor ST and a pair of semiconductor non-volatile memory elements ME
1
and ME
2
.
In each cell, the semiconductor non-volatile memory elements ME
1
and ME
2
have their respective drains connected to the source of the selecting transistor ST through an interconnection DL. A gate select line GL is connected to the gate of the selecting transistor ST and a bit line BL
0
is connected to its drain. Word lines WLa and WLb are connected to the control gates of the semiconductor non-volatile memory elements ME
1
and ME
2
, and a source line SL is connected to the sources of the two elements. A body line BD is connected to the bodies of the semiconductor non-volatile memory elements ME
1
and ME
2
. A plurality of such cells are arranged in the row direction to form the blocks B
0
to Bn and the blocks B
0
to Bn are arranged in the column direction to form the memory cell array AR.
A row decoder XD and a column decoder YD are connected to the address buffer AB. Further, a control block CB including a column selecting circuit, a sense amplifier and a page buffer is connected to the column decoder YD. The control block CB is connected also to the data input/output buffer DB. The gate select line GL, word lines WLa and WLb, source line SL and body line BD connected to the cells in the blocks B
0
to Bn in the memory cell array AR extend from the row decoder XD. Bit lines BL
0
to BLm connected to a plurality of cells in the memory cell array AR across the blocks B
0
to Bn extend from the control block CB.
The semiconductor storage device further comprises a microprocessor MP for controlling write and erase of information into and from the semiconductor non-volatile memory elements ME
1
and ME
2
, a positive charge pump circuit CPp for generating a positive high voltage and a negative charge pump circuit CPn for generating a negative high voltage, which are controlled by the microprocessor MP. It further comprises a word line boosting circuit BC for generating a high voltage on the word lines in operation of reading the stored contents. These high-voltage generating circuits operate only when needed, and become inactive in other operations such as standby operation so as not to consume wasteful power.
The outputs of the positive charge pump circuit CPp, negative charge pump circuit CPn and the word line boosting circuit BC are all inputted to a voltage select circuit VS. The voltage select circuit VS gives a positive high voltage for writing to the circuits in the control block CB through a voltage signal line VL
1
and also gives a positive or negative high voltage for writing, erasing and reading to the row decoder XD through voltage signal lines VL
2
.
In this semiconductor storage device, the present invention focuses on the word line boosting circuit BC. In the semiconductor storage device having semiconductor non-volatile memory elements, what is required for the word line boosting circuit BC is not simple generation of a high voltage. This is described referring to FIG.
30
.
FIG. 30
is a diagram showing threshold voltages required for channel formation in mass-produced semiconductor non-volatile memory elements and a distribution thereof. In
FIG. 30
, the horizontal axis shows the threshold voltage VTH and the vertical axis shows the distribution D (V
TH
).
In the case of an N-channel semiconductor non-volatile memory element, for example, its threshold voltage rises when electrons are injected to a floating electrode. In this example, a state in which electrons are injected to the floating electrode is regarded as “1” and a state in which electrons are not is regarded as “0.” The threshold voltage corresponding to “1” and the threshold voltage corresponding to “0” differ in different semiconductor non-volatile memory elements, which form a distribution as shown in FIG.
30
. The threshold voltage corresponding to “0” of the semiconductor non-volatile memory elements is set in the viewpoint of high-speed access and the threshold voltage corresponding to “1” is set in the viewpoint of securing read margin and reliability.
The values “0” and “1” of the semiconductor non-volatile memory elements are distinguished according to whether the threshold voltage is higher or lower than a reference voltage Vbs. Hence, if the value of the reference voltage Vbs is lower than the upper limit value V
1
of the distribution of the threshold voltages corresponding to “0,” then “0” may be erroneously determined to be “1.” Similarly, if the value of the reference voltage Vbs is higher than the lower limit value V
2
of the distribution of the threshold voltages corresponding to “1,” then “1” may be erroneously determined to be “0.” Therefore the reference voltage Vbs for determining the threshold voltage level must fall between the upper limit value V
1
and the lower limit value V
2
. That is to say, although the word line boosting circuit BC boosts the power-supply voltage, it should not boost it too high.
FIG. 31
is a diagram showing a conventional word line boosting circuit BCe. The word line boosting circuit BCe operates with a boost enable signal BE to generate the boosted voltage Vbs; it gives voltages boosted in the two boosting circuits HCe and VCe to the N-channel MOS transistor TR
1
. The word line boosting circuit BCe further comprises delay circuits D
1
and D
2
, a NOR gate NOG
1
, a NAND gate NAG
1
, and inverters Ih
1
, Ih
2
, Iv
1
and Iv
2
.
The boost enable signal BE is inputted to the delay circuits D
1
and D
2
and also to input ends of the NOR gate NOG
1
and NAND gate NAG
1
. The output DL
1
of the delay circuit D
1
is inputted to the other input end of the NOR gate NOG
1
and the output DL
2
of the delay circuit D
2
is inputted to the other input end of the NAND gate NAG
1
.
The output of the NOR gate NOG
1
passes through the inverter Ih
1
to become a gate boost enable signal HBE and the gate boost enable
Berhane Adolf Deneke
Mitsubishi Denki & Kabushiki Kaisha
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