Miscellaneous active electrical nonlinear devices – circuits – and – Specific identifiable device – circuit – or system – With specific source of supply or bias voltage
Reexamination Certificate
2001-12-06
2003-02-11
Lam, Tuan T. (Department: 2816)
Miscellaneous active electrical nonlinear devices, circuits, and
Specific identifiable device, circuit, or system
With specific source of supply or bias voltage
C327S535000, C327S536000
Reexamination Certificate
active
06518831
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a boosting circuit for a high voltage operation in a semiconductor memory device, and in particular to an improved boosting circuit for a high voltage operation which can prevent a transistor of a high voltage pump circuit from being destroyed due to an excessive bootstrap voltage in a pumping operation, by controlling the operation of the high voltage pump circuit according to a signal which detects when the bootstrap voltage of the high voltage pump circuit has increased above a predetermined level.
2. Description of the Background Art
In general, the DRAM is a random access memory for writing or reading data to/from a memory cell having one transistor and one capacitor. When a RAS bar signal /RAS which is a row address strobe signal is activated, the DRAM decodes an inputted row address to drive a selected word line.
Since the cell transistor composing the memory cell uses an NMOS, the DRAM includes a word line driving VPP generator for generating a potential of a power voltage VCC+a threshold voltage Vtn+&Dgr;V by considering a voltage loss due to the threshold voltage Vtn.
That is, a PMOS transistor successfully transmits a high potential, but it is difficult to transmit a low potential below the threshold voltage. An NMOS transistor successfully transmits a low potential, but it is difficult to transmit a potential higher than a potential which is lower than a gate potential by the threshold voltage. Therefore, when the NMOS transistor is used to decrease a size of the device or prevent a latch-up, a potential higher than a high potential transmitted to a gate of the NMOS transistor by at least the threshold voltage should be applied to successfully transmit the high potential. As a result, the high voltage VPP having a higher potential than the power voltage VCC is required to drive the word line of the DRAM.
FIG. 1
is a block diagram illustrating a conventional boosting circuit for a high voltage operation. Referring to
FIG. 1
, the conventional boosting circuit includes a VPP level detecting unit
10
, a VPP control circuit unit
20
, a ring oscillator unit
30
and a VPP pump unit
40
.
When an operation control signal BIE indicating that a high voltage operation mode has a high level, the VPP level detecting unit
10
compares the high voltage VPP with a reference voltage Vref, and outputs a signal VPBSB upon detecting that the high voltage VPP has reached a target value. Here, when the high voltage VPP is higher than the reference voltage Vref, the output signal VPBSB has a low level, thus preventing a VPP pumping operation. When the high voltage VPP is lower than the reference voltage Vref, the output signal VPBSB has a high level, thus performing the VPP pumping operation.
The VPP control circuit unit
20
receives the output signal VPBSB from the VPP level detecting unit
10
and the operation control signal BIE, and generates a signal OSCSW for controlling the operation of the ring oscillator unit
30
. When the output signal VPBSB from the VPP level detecting unit
10
and the operation control signal BIE have a high level, the VPP control circuit unit
20
generates the high level output signal OSCSW to operate the ring oscillator unit
30
. When any of the output signal VPBSB from the VPP level detecting unit
10
and the operation control signal BIE has a low level, the output signal OSCSW has a low level so as not to operate the ring oscillator unit
30
.
When the output signal OSCSW from the VPP control circuit unit
20
has a high level, the ring oscillator unit
30
performs an oscillation operation to generate a pulse signal BPOSC having a predetermined period. When the output signal OSCSW from the VPP control circuit unit
20
has a low level, the ring oscillator unit
30
is not operated.
The VPP pump unit
40
pumps electric charges until the VPP voltage reaches the target value according to the pulse signal BPOSC from the ring oscillator unit
30
.
That is, in the high voltage operation mode, the operation control signal BIE is enabled in a high level, and the ring oscillator unit
30
starts the operation. The VPP pump unit
40
is operated according to the pulse signal BPOSC from the ring oscillator unit
30
, thereby increasing the VPP voltage. Thereafter, the VPP level detecting unit
10
detects the VPP voltage, prevents the VPP pumping operation when the detected value reaches the target value, and facilitates the VPP pumping a operation when the detected value does not reach the target value. By repeating the procedure, the VPP voltage maintains a constant potential.
FIG. 2
is a circuit diagram illustrating the conventional VPP level detecting unit
10
of FIG.
1
. The VPP level detecting unit
10
includes: a PMOS transistor P
1
connected in a diode structure between the high voltage VPP and a node Nd
1
; a PMOS transistor P
2
being connected between the node Nd
1
and a node Nd
2
, having its gate connected to receive the power voltage VDD, and being turned on when a potential of the node Nd
1
is higher than the power voltage VDD; a PMOS transistor P
3
connected between the node Nd
2
and a node Nd
3
, and turned on when the operation control signal BIE has a high level, for transmitting the signal of the node Nd
2
to the node Nd
3
; an NMOS transistor N
1
connected in a diode structure between the node Nd
3
and a ground voltage VSS, and turned on when the signal of the node Nd
3
is higher than the threshold voltage Vt, for discharging the voltage of the node Nd
3
to the ground voltage VSS; and an NMOS transistor N
2
connected between the node Nd
3
and the ground voltage VSS, and turned on when the operation control signal BIE has a low level, thereby making the voltage at node Nd
4
a high level, for discharging the voltage of the node Nd
3
to the ground voltage VSS. In addition, the VPP level detecting unit
10
includes: a PMOS transistor P
4
being connected between the power voltage VDD and a node Nd
5
, and having its gate connected to receive the ground voltage VSS; NMOS transistors N
3
and N
4
connected in series between the node Nd
5
and the ground voltage VSS, and respectively controlled according to the signal of the node Nd
3
and the power voltage VDD; and inverters IV
1
and IV
2
connected in series between the node Nd
5
and a node Nd
6
outputting an output signal VPBSB.
In the, VPP level detecting unit
10
, when the operation control signal BIE has a high level, the PMOS transistor P
3
is turned on, and the NMOS transistor N
2
is turned off, to transmit ‘VPP—threshold value Vt of PMOS transistors P
1
-P
3
’ to the node Nd
3
. Here, when the VPP voltage exceeds ‘power voltage VDD+|2Vtp|’, the output signal VPBSB has a low level, thereby stopping the VPP pumping operation. Vtp denotes the threshold voltage of the PMOS transistors. Conversely, when the VPP voltage is lower than ‘power voltage VDD+|2Vtp|’, the output signal VPBSB has a high level, thereby performing a boosting operation for pumping the VPP voltage.
FIG. 3
is a circuit diagram illustrating the conventional
40
VPP control circuit unit
20
of FIG.
1
. The VPP control circuit unit
20
includes: a NAND gate NA
1
for receiving the output signal VPBSB from the VPP level detecting unit
10
and the operation control signal BIE; and inverters IV
3
-IV
5
connected in series between an output node Nd
7
of the NAND gate NA
1
and an output terminal Nd
8
outputting the signal OSCSW.
When the output signal VPBSB from the VPP level detecting unit
10
and the operation control signal BIE have a high level, the VPP control circuit unit
20
generates the high level output signal OSCSW. When the output signal OSCSW has a high level, the ring oscillator unit
30
is operated to pump the VPP voltage.
FIG. 4
is a circuit diagram illustrating the conventional ring oscillator unit
30
of FIG.
1
. The ring oscillator unit
30
includes: a NAND gate NA
2
for receiving the output signal OSCSW from the VPP control c
Hur Young Do
Ok Seung Han
Hynix / Semiconductor Inc.
Jacobson & Holman PLLC
Lam Tuan T.
Nguyen Hiep
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