Booster power management integrated circuit chip with ESD...

Details Booster power management integrated circuit chip with ESD... Booster power management integrated circuit chip with ESD...

2005-06-15

2008-10-14

Sherry, Michael J (Department: 2836)

Electricity: electrical systems and devices

Safety and protection of systems and devices

Load shunting by fault responsive means

Reexamination Certificate

active

07436640

ABSTRACT:
A booster power management integrated circuit chip includes first and second output pads, a transistor switch coupled between the first and second output pads and having a gate, and a trigger circuit coupled between the first and second output pads and further coupled to the gate of the transistor switch. The trigger circuit drives the transistor switch to conduct when an instantaneous voltage larger than a trigger voltage level is present between the first and second output pads so as to enable electric current to flow through the transistor switch.

REFERENCES:
patent: 5463520 (1995-10-01), Nelson
patent: 7102862 (2006-09-01), Lien et al.
patent: 2005/0057866 (2005-03-01), Mergens et al.

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