Miscellaneous active electrical nonlinear devices – circuits – and – Specific identifiable device – circuit – or system – With specific source of supply or bias voltage
Reexamination Certificate
2001-03-01
2003-02-25
Lam, Tuan T. (Department: 2816)
Miscellaneous active electrical nonlinear devices, circuits, and
Specific identifiable device, circuit, or system
With specific source of supply or bias voltage
C327S390000, C327S589000
Reexamination Certificate
active
06525595
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a booster for boosting a supplied voltage, an IC card having the same, and electronic equipment having the same. The present invention particularly relates to a booster for reducing a current peak and improving boosting efficiency, an IC card having the same, and electronic equipment having the same.
2. Description of the Related Art
Recently, a non-contact IC (integrated circuit) card has received attention as a recording medium. The non-contact IC card includes an EEPROM (Electrically Erasable Programmable Read Only Memory), receives by an antenna a high-frequency signal transmitted from a terminal equipment, and generates electricity for internal use.
FIG. 1
is a schematic diagram showing the relationship of voltages supplied to circuits in the non-contact IC card.
As shown in
FIG. 1
, a non-contact IC card
101
is provided with an RF circuit
102
, which extracts a data component from a signal received by the antenna and generates an internal source voltage Vdd. A central processing unit (CPU)
103
, an I/O circuit
104
, and a peripheral circuit
105
, which are operated by the internal source voltage Vdd, are further provided. The IC card
101
includes an EEPROM
106
for storing data and a charge pump
107
for generating a voltage Vpp, which is used for writing and deleting data in the EEPROM
106
. Additionally, a decoder and the like in the EEPROM
106
are operated by the internal source voltage Vdd. Moreover, the IC card
101
is provided with a voltage regulator
108
for reducing the internal source voltage Vdd to a voltage for charge pump Vcp, which is applied to the charge pump
107
, and a ring oscillator
109
for dividing the voltage for charge pump Vcp to produce a clock signal (frequency: about 4 to 8 MHz) of the charge pump
107
.
Further, normally, the internal source voltage Vdd is set at about 2.2 to 3.3 V, the voltage for charge pump Vcp is set at about 2.0 to 2.5 V, and the voltage Vpp is set about 12 to 13 V.
Also, the magnitude of electricity (internal source voltage Vdd) generated by receiving a high-frequency signal is determined by a distance between the terminal equipment and the non-contact IC card, the shape of the antenna, and the like. The efficiency of generating electricity is not so high. Hence, the IC card
101
includes a security circuit
110
for suspending the operation of the CPU
103
, the I/O circuit
104
, the peripheral circuit
105
, and the like to prevent malfunction thereof in the case of a drop in the internal source voltage Vdd.
A clock signal supplied to the CPU
103
is extracted from signals received in the RF circuit
102
, and the clock signal is inputted as an operating clock signal (control clock signal) to the I/O circuit
104
, the peripheral circuit
105
, the security circuit
110
, and the voltage regulator
108
as well as the CPU
103
.
FIG. 2
is a circuit diagram showing an example of a conventional charge pump.
In the conventional charge pump, for example, a plurality of transistors Tr
100
, Tr
101
, Tr
102
, Tr
103
, Tr
104
, and the like are connected in series. A voltage for charge pump Vcp is supplied to the gate and source of the transistor Tr
100
. Further, capacitors C
101
, C
102
, C
103
, C
104
, and the like each have a terminal connected to each node provided between the adjacent transistors. Inverters IV
101
, IV
102
, IV
103
, IV
104
, and the like are respectively connected to the other terminals of the capacitors. A clock signal CLK oscillated by the ring oscillator
109
is inputted to the inverters IV
101
, IV
103
, and the like, and an inverted signal CLKB of the clock signal CLK is inputted to the inverters IV
102
, IV
104
, and the like. Therefore, the inverters IV
101
, IV
103
, and the like are simultaneously driven and the inverters IV
102
, IV
104
, and the like are simultaneously driven. Additionally, the clock signal CLK in
FIG. 2
corresponds to the clock signal CLK shown in FIG.
1
.
Moreover, Japanese Patent Laid-Open Publication No. Hei 2-62796 discloses a booster in which inverters are connected in series.
FIG. 3
is a circuit diagram showing the booster disclosed in this publication.
In the booster of the publication as well, a plurality of transistors Tr
110
, Tr
111
, Tr
112
, Tr
113
, Tr
114
, and the like are connected in series, and a source voltage is supplied to the gate and source of the transistor Tr
110
. Also, capacitors C
111
, C
112
, C
113
, C
114
, and the like each have a terminal connected to each of the nodes. Each of the nodes is provided between the adjacent transistors. Inverters IV
111
, IV
112
, IV
113
, IV
114
, and the like are connected to the other terminals of the capacitors. Here, the inverters IV
111
, IV
112
, IV
113
, IV
114
, and the like are connected in series, and a clock signal CLK is inputted to the inverter IV
111
on the first stage. Therefore, a signal in opposite phase with the clock signal CLK is inputted to the transistors Tr
111
, Tr
113
, and the like, and a signal in phase with the clock signal CLK is inputted to the transistors Tr
112
, Tr
114
, and the like. Hence, the inverters IV
111
, IV
113
, and the like are simultaneously driven and the inverters IV
112
, IV
114
, and the like are simultaneously driven. However, the inverters connected in series cause delay of a clock signal, so that the transistors are gradually shifted from one another in operational timing. Additionally, the clock signal CLK in
FIG. 3
corresponds to the clock signal CLK shown in FIG.
1
.
However, in the conventional charge pump shown in
FIG. 2
, about a half of the transistors are driven by one clock signal, so that a clock driver handles heavy load. A large number of clock drivers are simultaneously operated, resulting in an extremely high peak of source current on the rising of a clock signal. Namely, when source current has an extremely high peak, electricity supplied to the voltage regulator
108
rapidly increases at the moment and electricity supplied to the other circuits rapidly decreases. Although the security circuit
110
can detect a relatively mild reduction in electricity to prevent malfunction of the other circuits, the security circuit
110
cannot detect the above rapid reduction to suspend the operation of the circuit such as the CPU
103
. For this reason, in the case of a high peak of source current, malfunction is likely to occur in the CPU
103
and the like.
Meanwhile, in the conventional booster shown in
FIG. 3
, the inverters IV
111
and the like are connected with delays and driving function. Hence, when the delay is reduced by shortening a clock period to shorten boosting time, current of the following stage is superposed to that of the previous stage. Consequently, the amount of current increases with later stages. Thus, a peak of current cannot be sufficiently reduced and is increased with the number of stages.
Furthermore, Japanese Patent Laid-Open Publication No. Hei 11-164545 discloses a charge pump in which a plurality of charge pump stages are provided and are shifted from one another in operation. Although a current peak is smaller than that of the precedent applications, the reduction is not sufficient. Moreover, a high period coincides with that of a clock signal on the following stage, so that charging and discharging times cannot be sufficiently obtained, resulting in lower booster efficiency.
SUMMARY OF THE INVENTION
An object of the present invention is to provide a booster being capable of preventing malfunction of other circuits in a non-contact IC card by reducing a current peak, an IC card having the same, and electronic equipment having the same.
According to the present invention, a booster comprises first to k-th (k is an even number) transistors connected to one another in series, first to k-th capacitors each having an end connected to the gate and source of each of the first to k-th transistors, and a clock driver which supplies clock signals out of phase with one another to the other ends of the firs
Lam Tuan T.
NEC Corporation
Nguyen Hiep
Sughrue & Mion, PLLC
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