Static information storage and retrieval – Floating gate – Particular biasing
Reexamination Certificate
2005-05-31
2005-05-31
Lam, David (Department: 2818)
Static information storage and retrieval
Floating gate
Particular biasing
C365S185210, C365S189110
Reexamination Certificate
active
06901009
ABSTRACT:
A detection circuit detects a rising time period between a power supply ON time or a reset time and a time when a boosted voltage reaches a standby voltage, and outputs a detection signal representing a result of the detection. An oscillation circuit generates an outputs a clock signal having a constant frequency which is lower than a frequency in an ordinary state, while the detection signal is at a high level. A charge pump circuit boosts a power source voltage in response to the input clock signal of the constant frequency and causes the boosted voltage to gently rise from the power source voltage, thereby effectively interfering with an increase in reference voltage accompanied by the increase in boosted voltage.
REFERENCES:
patent: 5408115 (1995-04-01), Chang
patent: 5422504 (1995-06-01), Chang et al.
patent: 5494838 (1996-02-01), Chang et al.
patent: 5563824 (1996-10-01), Miyawaki et al.
patent: 5969383 (1999-10-01), Chang et al.
patent: 6177318 (2001-01-01), Ogura et al.
patent: 6248633 (2001-06-01), Ogura et al.
patent: 6255166 (2001-07-01), Ogura et al.
patent: A 7-161851 (1995-06-01), None
patent: B1 2978477 (1999-09-01), None
patent: A 2001-156188 (2001-06-01), None
U.S. patent application Ser. No. 09/955,158, Kanai et al., filed Sep. 19, 2001.
U.S. patent application Ser. No. 09/955,160, Kanai et al., filed Sep. 19, 2001.
U.S. patent application Ser. No. 10/115,913, Kamei, filed Apr. 5, 2002.
U.S. patent application Ser. No. 10/115,956, Kamei, filed Apr. 5, 2002.
U.S. patent application Ser. No. 10/153,611, Owa, filed May 24, 2002.
U.S. patent application Ser. No. 10/153,686, Owa, filed May 24, 2002.
U.S. patent application Ser. No. 10/153,736, Owa, filed May 24, 2002.
U.S. patent application Ser. No. 10/157,896, Kamei et al., filed May 31, 2002.
U.S. patent application Ser. No. 10/157,897, Kamei et al., filed May 31, 2002.
U.S. patent application Ser. No. 10/193,066, Kanai, filed Jul. 12, 2002.
U.S. patent application Ser. No. 10/193,602, Kanai, filed Jul. 12, 2002.
U.S. patent application Ser. No. 10/197,643, Kanai et al., filed Jul. 18, 2002.
U.S. patent application Ser. No. 10/197,644, Kamei, filed Jul. 18, 2002.
U.S. patent application Ser. No. 10/197,645, Natori, filed Jul. 18, 2002.
U.S. patent application Ser. No. 10/197,646, Kanai, filed Jul. 18, 2002.
U.S. patent application Ser. No. 10/197,668, Kanai, filed Jul. 18, 2002.
U.S. patent application Ser. No. 10/229,064, Kamei, filed Aug. 28, 2002.
U.S. patent application Ser. No. 10/246,486, Natori, filed Sep. 19, 2002.
U.S. patent application Ser. No. 10/246,665, Natori, filed Sep. 19, 2002.
U.S. patent application Ser. No. 10/246,708, Natori, filed Sep. 19, 2002.
U.S. patent application Ser. No. 10/246,727, Natori, filed Sep. 19, 2002.
U.S. patent application Ser. No. 10/323,921, Natori, filed Dec. 20, 2002.
Hayashi et al., “Twin MONOS Cell with Dual Control Gates”, 2000 IEEE VLSI Technology Digest of Technical Papers.
Chang et al., “A New SONOS Memory Using Source-Side Injection for Programming”, IEEE Electron Device Letters, vol. 19, No. 7, Jul. 1998, pp. 253-255.
Chen et al., “A Novel Flash Memory Device with S Plit Gate Source Side Injection and ONO Charge Storage Stack (SPIN)”, 1997, VLSI Technology Digest, pp. 63-64.
Lam David
Oliff & Berridg,e PLC
Seiko Epson Corporation
LandOfFree
Booster circuit for non-volatile semiconductor memory device does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Booster circuit for non-volatile semiconductor memory device, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Booster circuit for non-volatile semiconductor memory device will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3401954