Booster circuit for a semiconductor memory device

Details Booster circuit for a semiconductor memory device Booster circuit for a semiconductor memory device

1991-05-29

1992-07-28

Hudspeth, David

Electrical transmission or interconnection systems

Nonlinear reactor systems

Parametrons

307269, 307270, 365203, H03K 1901

Patent

active

051343177

ABSTRACT:
The secondary side of a control capacitor is charged, prior to the precharge period, almost to the source voltage level by a dummy cycle performed after power-on. Then, during the precharge period, a control circuit charges the control capacitor to increase the potential of its primary side to a level higher than the source voltage level V.sub.cc. The potential of the gate of the first transistor is increased to a level higher than the source voltage level, which causes the first transistor to turn on to charge a booster capacitor. At this time, since the secondary side of the booster capacitor is grounded through a third transistor, the primary side of the booster capacitor is held at the source voltage level. When the active period is entered, the third transistor is turned off, and a second transistor which is connected between the power source and the booster capacitor is turned on. This causes the potential of the secondary side of the booster capacitor to rise to the source voltage level. The control circuit operates to ground the control terminal of the first transistor so that the first transistor is turned off, thereby increasing the potential of the primary side of the booster capacitor to a level higher than the source voltage level. The signal of the level higher than the source voltage level is output from the output terminal through a fourth transistor.

REFERENCES:
patent: 4484092 (1984-11-01), Campbell
patent: 4503522 (1985-03-01), Etoh et al.
patent: 4677313 (1987-06-01), Mimoto
patent: 4678941 (1987-07-01), Chao et al.
patent: 4704706 (1987-11-01), Nakano et al.
patent: 4906056 (1990-03-01), Taniguchi

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