Miscellaneous active electrical nonlinear devices – circuits – and – Specific identifiable device – circuit – or system – With specific source of supply or bias voltage
Reexamination Certificate
2002-07-23
2004-07-13
Cunningham, Terry D. (Department: 2816)
Miscellaneous active electrical nonlinear devices, circuits, and
Specific identifiable device, circuit, or system
With specific source of supply or bias voltage
Reexamination Certificate
active
06762639
ABSTRACT:
BACKGROUND OF THE INVENTION
This invention relates to a booster circuit contained in a semiconductor device and, more particularly, to a booster circuit used as an internal power supply for a dynamic random access memories (DRAM) for use in a portable apparatus driven by an external power supply of 1.8V and a driving method thereof.
Generally, a booster circuit of the type described (which will be called hereafter “a normal pump circuit”) comprises a pump capacitor, switches, and a power supply. The normal pump circuit has a current (charge) efficiency of about 50%.
In order to realize a low power consumption, a booster circuit (a pump circuit) having an improved current (charge) efficiency more than 50% is described or disclosed in Japanese Unexamined Patent Publication Tokkai No. Hei 9-231,752 or JP-A 9-231752. The booster circuit (pump circuit) disclosed in JP-A 9-231752 comprises two pump capacitors and five switches.
In the manner which will later be described in conjunction with
FIGS. 1A and 1B
, the booster circuit disclosed in JP-A 9-231752 comprises a first pump capacitor, a second pump capacitor, and first through fifth switches. The booster circuit is supplied with a power-supply voltage (power-supply potential) and a ground voltage (ground potential). The booster circuit produces (generates) a boosted level (boosted potential). That is, the booster circuit has a node supplied with the power-supply voltage, a node supplied with the ground voltage, and a node for generating the boosted level. The node supplied with the power-supply voltage is called a “power-supply node”. The node supplied with the ground voltage is called a “ground node”. The node for generating the boosted level is called a “booster node”. In addition, the booster circuit has first and second input nodes and first and second intermediate nodes.
The first pump capacitor is connected between the first input node and the first intermediate node. The second pump capacitor is connected between the second input node and the second intermediate node.
The first through the third switches are connected in series between the power-supply node and the ground node. Specifically, the first switch is connected between the power-supply node and the first input node. Generally, the first switch comprises a P-channel metal oxide semiconductor (PMOS) transistor which has a source connected to the power-supply node and a drain connected to the first input node. The second switch is connected between the first input node and the second input node. Generally, the second switch comprises an N-channel metal oxide semiconductor (NMOS) transistor which has a drain connected to the first input node and a source connected to the second input node. The third switch is connected between the second input node and the ground node. Generally, the third switch comprises an NMOS transistor which has a drain connected to the second input node and a source connected to the ground node.
The fourth switch has a fixed contact fixedly connected to the first intermediate node and a moving contact which is selectively connected to either the power-supply node or the booster node. The fifth switch has a fixed contact fixedly connected to the second intermediate node and a moving contact which is selectively connected to either the power-supply node or the booster node.
The booster circuit having such structure repeats a first state and a second state to realize high efficiency of booster and a supply current. The first state is a state where the first pump capacitor discharges and the second pump capacitor is charged. On the other hand, the second state is a state where the first pump capacitor is charged and the second pump capacitor discharges.
More specifically, in the first state, the first switch is turned on or makes, the second switch is turned off or breaks, the third switch is turned on or makes, the fourth switch connects the first intermediate node with the booster node, and the fifth switch connected the second intermediate node with the power-supply node. In this state, the first pump capacitor is climbed by the power-supply voltage to supply the booster node with a current. Simultaneously, the second pump capacitor is charged by the power-supply voltage and the ground voltage.
On the other hand, in the second state, the first switch is turned off or breaks, the second switch is turned on or makes, the third switch is turned off or breaks, the fourth switch connects the first intermediate node with the power-supply node, and the fifth switch connects the second intermediate node with the booster node. In this state, the first and the second pump capacitors are connected to each other in series, the first pump capacitor is climbed by the power-supply voltage, and a current flows from the second pump capacitor to the booster node. In this event, inasmuch as the first pump capacitor has an electrode direction in the opposite direction to a booster direction, the first pump capacitor is charged with charges moved.
It is assumed that the amount of charges moving for a half cycle per capacitor is represented by &Dgr;Q. In this event, the amount of charges flowing out of the power-supply node is equal to 3 &Dgr;Q. On the other hand, the amount of charges supplied to the booster node is equal to 2 &Dgr;Q. Accordingly, the booster circuit has a current (charge) efficiency of about 66.6% or two-thirds. In comparison with the normal pump circuit having the current (charge) efficiency of about 50%, the booster circuit has an improved current (charge) efficiency about 1.33 times.
However, the above-mentioned booster circuit disclosed in JP-A 9-231752 is disadvantageous in that a voltage enable to boost is limited to 1.5 times the power-supply voltage. Therefore, a supply current drastically decreases when the boosted level approaches 1.3 times the power-supply voltage and a supply efficiency deteriorates. A ground occurring this problem will later be described in conjunction with FIG.
2
.
In addition, various booster circuits except for the above-mentioned one are proposed. By way of example, WO98/44621 discloses a power-supply circuit which is capable of variably controlling a boosting ratio by means of two pump capacitors and five switches. More specifically, a power course circuit can reduce its own power consumption and can select its boosting ratio in accordance with the duty ratio. The power source circuit comprises a charge pump circuit including a first switching section which accumulates charges in a first capacitor and a second switching section which transfers the charges accumulated in the first capacitor to a second capacitor, and a circuit which generates switching signals for controlling the first and the second switching sections. The first switching section comprises first and second switching elements which are respectively connected to different potentials on one side and to one end of the first capacitor on the other side. The switching signal generating circuit variably controls the boosting rate by turning on or off the first switching element and turning off the second switching element or by turning on or off the second switching element and turning off the first switching element. The potential of the switching signal when the first and the second switching elements are turned off is made equal to the potential supplied to the source of a switching transistor. The boosting rate is controlled in accordance with the duty ratio when a liquid crystal display is operated for partial display.
U.S. Pat. No. 6,259,612 issued to Yasuo Itoh discloses a semiconductor integrated circuit having a small chip area using two pump capacitors. According to Itoh, an internal voltage generator generates an internal voltage that is obtained by up-converting or down-converting an external power supply voltage. A resistor-voltage divider, having a plurality of resistors, outputs a first divided voltage that is obtained by dividing the internal voltage according to a resistance ratio of the resistors. A capacitor-voltage divider, having
Hashimoto Takeshi
Ito Yutaka
Choate Hall & Stewart
Cunningham Terry D.
Elpida Memory Inc.
Tra Quan
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