Booster circuit

Details Booster circuit Booster circuit

2002-12-17

2004-06-29

Zweizig, Jeffrey (Department: 2816)

Miscellaneous active electrical nonlinear devices, circuits, and

Specific identifiable device, circuit, or system

With specific source of supply or bias voltage

Reexamination Certificate

active

06756837

ABSTRACT:

BACKGROUND OF THE INVENTION
The present invention relates to booster circuits used for nonvolatile semiconductor memories and semiconductor integrated circuits.
In recent years, in nonvolatile semiconductor memories such as flash EEPROMs, booster circuits have been widely used for supply of various levels of high voltages for write, erase and read operations. In particular, as such booster circuits, used extensively are threshold-offset type booster circuits driven with a four-phase clock signal that are excellent in low-voltage operation and boost efficiency.
A conventional four-phase clock driven threshold-offset type booster circuit will be described with reference to FIG.
21
. The booster circuit of
FIG. 21
is a four-stage booster circuit including four booster cells
1
a
to
1
d
connected in series. A rectifying transistor Md is connected to the output of the final-stage booster cell
1
d
for outputting an output voltage VPP. A limit circuit
2
and a smoothing capacitor Co are connected to the output of the rectifying transistor Md. The limit circuit
2
is essentially composed of a read Zener diode DZ
1
having a breakdown voltage of 5V used for read operation, a rewrite Zener diode DZ
2
having a breakdown voltage of 10V used for write/erase operations, and a switch
3
. By controlling the switch
3
with a switch control signal ACTH, the output voltage VPP is switched between 10V and 5V.
Each of the booster cells
1
a
to
1
d
is driven with two boost clock signals having different phases (CLK
1
and CLK
3
or CLK
2
and CLK
4
) as shown in FIG.
22
. The clock signals CKL
1
to CKL
4
are square waves having predetermined “H” and “L” durations and cycles. The booster cells
1
a
to
1
d
have an identical configuration to each other, which may be that disclosed in Japanese Laid-Open Patent Publication No. 2001-268893, for example.
FIG. 23
shows an example of internal configuration of the final-stage booster cell
1
d
. Referring to
FIG. 23
, the booster cell
1
d
includes an N-channel charge-transfer transistor M
1
, an N-channel switching transistor M
2
and two boost capacitors C
1
and C
2
. The booster cell
1
d
receives the clock signal CLK
4
at one clock terminal CLKS, an inverted signal NCLK
2
of the clock signal CLK
2
at the other clock terminal CLKM, and a boosted voltage from the preceding-stage booster cell
1
c
at an input terminal VIN, and outputs a boosted voltage from an output terminal VO to the rectifying transistor Md.
The operation of the conventional booster circuit having the configuration described above will be described.
In the booster circuit of
FIG. 21
, charge is stored in the boost capacitors C
1
of the booster cells sequentially, starting from the first-stage booster cell
1
a
to the second-stage, third-stage and fourth-stage cells, to finally obtain an arbitrary high voltage. For example, a voltage boosted in the third-stage booster cell
1
c
is transferred from the boost capacitor C
1
of the third-stage booster cell
1
c
to the boost capacitor C
1
of the fourth-stage booster cell
1
d
. During this voltage transfer, in the final-stage booster cell
1
d
, the boost clock signal CLK
4
input to the boost capacitor C
2
is changed from the ground potential to the supply potential at timing T6 shown in
FIG. 22
, so that the gate voltage of the charge-transfer transistor M
1
is sufficiently increased. With the sufficiently high gate voltage, it is possible to prevent voltage drop occurring when the boosted voltage is transferred from the third stage to the boost capacitor C
1
via the charge-transfer transistor M
1
. Thereafter, at timing T8, the inverted clock signal NCLK
2
input to the clock terminal CLKM is changed from the ground potential to the supply potential (that is, the clock signal CLK
2
is changed from the supply potential to the ground potential), so that the boosted voltage transferred to the boost capacitor C
1
is further boosted. By repeating this boost operation sequentially in the first to fourth stages, a boosted voltage higher than the supply voltage Vcc can be generated. In the fourth-stage booster cell
1
d
, at timing T8 in the next cycle, in which the inverted clock signal NCLK
2
input to the clock terminal CLKM of the fourth-stage booster cell
1
d
is changed from the ground potential to the supply potential (that is, the clock signal CLK
2
is changed from the supply potential to the ground potential), the gate-source voltage Vgs of the switching transistor M
2
exceeds the threshold voltage Vth of this transistor, turning ON the switching transistor M
2
. In this state, the charge at the gate of the charge-transfer transistor M
1
can be drawn to the input terminal VIN, and thus the gate voltage of this transistor decreases.
The limit circuit
2
can change the output voltage VPP to a predetermined voltage in response to the switch control signal ACTH. To state specifically, during write operation requiring a high voltage, the switch control signal ACTH is asserted, to connect the rewrite Zener diode DZ
2
to the output terminal of the booster circuit so that the output voltage VPP is clamped to 10V. During read operation requiring a low voltage, the switch control signal ACTH is negated, to connect the read Zener diode DZ
1
to the output terminal of the booster circuit so that the output voltage VPP is clamped to 5V. In this way, the output voltage VPP of the booster circuit can be changed according to the operation mode before supply for use.
However, it has been found that, as the voltage level of the power supply is made lower in the future, the conventional booster circuit described above will have a problem as follows when the output boosted voltage is abruptly switched from a high voltage to a low voltage, such as during a specific mode transition including transition from the data rewrite mode to the read mode and transition from the rewrite mode to the program verify mode, and during an instantaneous power interruption.
That is, referring to
FIG. 24
, during a specific mode transition or during an instantaneous power interruption as described above, in which the boosted voltage is switched to a low voltage, the source voltage Vs of the ON-state charge-transfer transistor M
1
of the fourth-stage booster cell
1
d
abruptly decreases, and with this, the drain voltage Vd also abruptly decreases, resulting in that the source voltage Vs and the drain voltage Vd become roughly an identical potential. Thus, the gate voltage Vg of the switching transistor M
2
and the source voltage Vs of the same transistor (that is, the drain voltage Vd of the charge-transfer transistor M
1
) become an identical potential. As a result, the switching transistor M
2
is cut off, leaving the gate of the charge-transfer transistor M
1
at a high voltage.
If the power supply is at a high voltage, that is, the amplitude of the boost clocks CLK
1
to CLK
4
is large, the fourth-stage booster cell
1
d
will operate as follows. When the inverted clock NCLK
2
of the boost clock CLK
2
is input to the terminal CLKM of the booster cell
1
d
, the gate voltage Vg of the switching transistor M
2
becomes sufficiently high due to the H level of the inverted clock NCLK
2
. Therefore, the gate-source voltage Vgs of the switching transistor M
2
exceeds the threshold voltage, turning ON the switching transistor M
2
. As a result, the charge at the gate of the charge-transfer transistor M
1
is released, preventing the gate from being left at a high voltage.
On the contrary, if the power supply is at a low voltage, the amplitude of the boost clocks CLK
1
to CLK
4
is small. Therefore, when the inverted clock NCLK
2
of the boost clock CLK
2
is input, the gate voltage Vg of the switching transistor M
2
fails to become sufficiently high due to the H level of the inverted clock NCLK
2
. Thus, the gate-source voltage Vgs of the switching transistor M
2
may not exceed the threshold voltage Vt. In this case, the switching transistor M
2
remains in the cut-off state irrespective of changes of the boost clocks CLK

Affiliated with

Also associated with

Rating

Booster circuit does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Booster circuit, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Booster circuit will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-3306596