Coded data generation or conversion – Sample and hold
Reexamination Certificate
2001-06-18
2003-02-11
Williams, Howard L. (Department: 2819)
Coded data generation or conversion
Sample and hold
C327S091000, C327S589000
Reexamination Certificate
active
06518901
ABSTRACT:
TECHNICAL FIELD
The present invention relates to a boosted switch device for a sampler of an analog/digital converter, and to an operating method thereof.
BACKGROUND OF THE INVENTION
As is known, broadly speaking, analog/digital conversion systems can be subdivided into two main categories, according to the conversion principle on the basis of which they operate: the first category includes the so-called Nyquist analog/digital conversion systems, which can be schematized with a continuous-time anti-aliasing filter, a switched-capacitor channel filter, and a Nyquist analog/digital converter, which are connected to one another in cascade, whereas the second category includes the so-called over-sampling analog/digital conversion systems, which can be schematized with a continuous-time anti-aliasing filter, an over-sampling analog/digital converter, and a digital channel filter which are connected to one another in cascade.
However, both categories carry out the conversion of an analog signal, i.e., of a signal which is continuous in time and in amplitude, into a sampled data signal, i.e., which is continuous in time and discrete in amplitude, by means of a so-called sampler.
FIG. 1
shows the general circuit diagram of the sampler which is best known and most commonly used in the applications.
In particular, as illustrated in
FIG. 1
, the sampler, indicated as a whole by
1
, comprises an input terminal
2
, at which there is present an input voltage V
A
to be sampled; an output terminal
4
; a sampling capacitor
6
connected between a first and a second node
8
,
10
; a first switch device
12
controlled by a first control signal F
1
D, and connected between the input terminal
2
of the sampler
1
and the first node
8
; a second switch device
14
controlled by a second control signal F
2
D, and connected between the first node
8
and a ground line
16
set to a ground potential V
GND
, typically 0 V; a third switch device
18
controlled by a third control signal F
1
, and connected between the second node
10
and the ground line
16
; and a fourth switch device
20
controlled by a fourth control signal F
2
, and connected between the output terminal
4
of the sampler
1
, and the second node
10
.
The output terminal
4
of the sampler is then typically connected to the virtual ground of an operational amplifier (not shown), with which it forms a switched-capacitor integrator.
On the other hand,
FIG. 2
shows the temporal development of the four control signals F
1
, F
2
, F
1
D, F
2
D, which are commonly also known as “phases,” and are supplied to the switch devices
12
,
14
,
18
,
20
of the sampler
1
. In particular, it can be noted that the first and the second control signals F
1
D and F
2
D are exact replicas respectively of the third and fourth control signals, which are temporally delayed compared with the latter, by a delay T
R
of approximately a few nanoseconds.
In addition, in order to guarantee correct operation of the sampler
1
, the first and second control signals F
1
D and F
2
D do not overlap one another temporally, in other words the first and second control signals F
1
D and F
2
D never assume a high logic level simultaneously, just as the third and fourth control signals F
1
and F
2
do not overlap one another temporally. In addition, neither the first and fourth control signals F
1
D, F
2
, nor the second and third control signals F
2
D, F
1
overlap one another temporally.
The operation of the sampler
1
is known, and will thus be described here briefly and only to the extent necessary for understanding of the problem on which the present invention is based.
In particular, according to the logic levels assumed by the control signals F
1
, F
2
, F
1
D and F
2
D, the sampler capacitor
6
is connected cyclically and in an alternating manner between the input terminal
2
and the ground line
16
, and between the latter and the output terminal
4
. In detail, when the first and the fourth control signals F
1
, F
1
D assume a high logic level, the input voltage V
A
is sampled, and the sample is stored in the sampler capacitor
6
, whereas when the second and the third control signal F
2
, F
2
D assume a high logic level, the sample of the input voltage V
A
which is stored in the sampler capacitor
6
is transferred to the output terminal
4
of the sampler
1
, and consequently to the virtual ground of the operational amplifier, with which it forms the aforementioned switched-capacitor integrator.
The use of four control signals having the timings shown in
FIG. 2
has been proposed in “Low-Distortion Switched-Capacitor Filter Design Techniques,” Kuang-Lu Lee and Robert G. Mayer, IEEE Journal of Solid-State Circuits, vol. sc-20, No. 6, December 1985, Section III B, pages 1103-1112, in order to overcome the disadvantages of the prior art samplers, in which the first and second switch devices
12
,
14
are controlled respectively by the control signal F
1
and by the control signal F
2
, instead of by their temporally delayed replicas.
In particular, the prior art samplers had the disadvantage that they introduced onto the output signal V
B
unacceptable distortions, generated mainly by the switch devices
12
,
14
,
18
,
20
. In fact, since these switch devices are not ideal, but have capacitances, and thus associated charges, which vary strongly according to the input voltage V
A
, at the instant at which these switch devices open, they introduce onto the output signal V
B
distortions which detract considerably from the performance of the sampler.
As demonstrated in the aforementioned article, by using instead, the control signals shown in
FIG. 2
with the structure shown in
FIG. 1
, the distortion of the output signal V
B
is strongly reduced, for input frequencies lower than 10 kHz, i.e., for harmonics of the input voltage V
A
with frequencies lower than 10 kHz.
However, at high frequencies, and in particular at input frequencies greater than 100 kHz, there is an ever greater increase in other distortions caused mainly by the circuit structure of the first switch device
12
, and on which the solution proposed in the aforementioned article does not have any effect, as explained in depth in “A Cascaded Sigma-Delta Pipeline A/D Converter with 1.25 MHz Signal Bandwidth and 89 dB SNR,” Todd L. Brooks, David H. Robertoson, Daniel F. Kelly, Anthony Del Muro and Stephen W. Harston, IEEE Journal Solid-State Circuits, vol. 32, No. 12, December 1997, Section IV B, pages 1896-1905.
In particular, according to the prior art, the first switch device
12
was usually formed by a CMOS transfer-gate switch having the circuit structure shown in
FIG. 3
, i.e., formed by an NMOS transistor
22
and by a PMOS transistor
24
having drain terminals connected to one another and to the input terminal
2
of the sampler
1
, source terminals connected to one another and to the first node
8
, and gate terminals receiving respectively the first control signal F
1
D and the first inverted control signal {overscore (F
1
D)}, the latter being generated by means of a logic inverter (not shown).
As explained in the aforementioned article, the switch devices with the circuit structure shown in
FIG. 3
have series resistances that vary considerably according to the input voltage V
A
, thus causing strong distortions at a high frequency.
In order to overcome the limitations inherent in the switch devices having the circuit structure shown in
FIG. 3
, in the aforementioned article, a switch device having the circuit structure shown in
FIG. 4
is proposed, which, for the reasons given hereinafter, is commonly known as “bootstrapped clock-boosted switch.”
In particular, as shown in this Figure, the switch device, indicated as a whole by 12′, comprises an NMOS transistor
30
having a drain terminal connected to the input terminal
2
of the sampler
1
, a source terminal connected to the first node
8
of the sampler
1
, and a gate terminal connected to a third node
32
; a PMOS transistor
34
having a drain terminal connected to the third node
32
,
Nicollini Germano
Pinna Carlo
Bennett II Harold H.
Jorgenson Lisa K.
Seed IP Law Group PLLC
STMicroelectronics S.r.l.
Williams Howard L.
LandOfFree
Boosted switch device for a sampler of an analog/digital... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Boosted switch device for a sampler of an analog/digital..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Boosted switch device for a sampler of an analog/digital... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3167327