Boosted potential generating circuit

Details Boosted potential generating circuit Boosted potential generating circuit

1995-06-27

2001-09-11

Cunningham, Terry D. (Department: 2816)

Miscellaneous active electrical nonlinear devices, circuits, and

Specific identifiable device, circuit, or system

With specific source of supply or bias voltage

C327S537000

Reexamination Certificate

active

06288601

ABSTRACT:

TECHNICAL FIELD
The present invention relates to a boosted potential generating circuit. The present invention has particular application to a semiconductor memory device, such as a dynamic random access memory (DRAM), for feeding the word lines with a boosted potential with respect to a power supply potential.
BACKGROUND ART
FIGS. 6-9
show a conventional boosted potential generating circuit. In
FIG. 6
, the boosted potential generating circuit has a clock input node
1
for receiving a clock (CLK) signal of binary levels consisting of a ground potential (0V) and a power supply potential (Vcc), as shown in FIG.
8
(
a
), and a boosted potential node
2
for supplying a boosted potential. A load capacitor
3
is driven by the boosted potential supplied to the boosted potential node
2
, and the load capacitor
3
is a parasitic capacitance existing between the boosted potential node and the ground potential node. An N-channel type MOS transistor
4
serves as a drive transistor for the boosted potential generating circuit, and is connected between the boosted potential node
2
and a first node
5
. A gate electrode is connected to a second node
6
, and a back gate (a p-well region
12
in
FIG. 7
) is connected to an output node of potential generating means (not shown) for outputting a negative potential Vbb.
A first buffer means
7
receives the clock signal from the clock input node
1
and outputs a first signal in phase with the clock signal. The first buffer means
7
comprises an even number of stages, or in this example, inverters
7
a
and
7
b
of two stages. A first capacitive element
8
has a pair of electrodes, where one electrode receives the first signal from the first buffer means
7
and the other electrode is connected to the first node
5
. A second buffer means
9
receives the clock signal from the clock input node
1
and outputs a second signal in phase with the clock signal. The second buffer means
9
comprises an even number of stages, or in this example, inverts
9
a
and
9
b
of two stages. A second capacitor
10
has a pair of electrodes, where one electrode receives the second signal from the second buffer means
9
and the other electrode is connected to the second node
6
.
FIG. 7
illustrates the boosted potential generating circuit incorporated in a semiconductor memory device, such as a dynamic random access memory (DRAM), with the N-channel type MOS transistor
4
having a pair of source and drain regions
13
and
14
formed in a p-well region
12
formed on a major surface of a semiconductor substrate
11
, and a gate electrode
15
. Since the semiconductor substrate
11
is supplied with the negative potential Vbb, the negative potential Vbb is also supplied back gate of the N-channel type MOS transistor
4
. In
FIG. 7
, a P-channel type MOS transistor is also fabricated with the N-channel type MOS transistor
4
. The P-channel type MOS transistor comprises a pair of source and drain regions
17
and
18
formed in an n-well region
16
formed on the major surface of a semiconductor substrate
11
, and a gate electrode
19
. Such a structure is generally referred to as a twin well structure. An oxide film
20
surrounds an element forming region to electrically isolate the elements.
The first and second nodes
5
and
6
in
FIG. 6
are precharged to the power supply potential Vcc (or a potential lower than the power supply potential by a threshold voltage of a MOS transistor) prior to application of the boosted potential to the boosted potential node
2
by a precharge means (not shown). Before the boosted potential is supplied to the boosted potential node
2
(or before time T
0
shown in FIG.
8
), the first and second nodes
5
and
6
are precharged to the power supply potential Vcc by the precharge means. As a result, the potential of the boosted potential node
2
is set at Vcc−Vth
4
by conduction of the N-channel type MOS transistor
4
, where Vth
4
is a threshold voltage of the N-channel type MOS transistor. Referring to a waveform diagram shown in
FIG. 8
, the operation of the boosted potential generating circuit is as follows.
At time T
0
, i.e., when the clock signal shown in FIG.
8
(
a
) is fed to the clock input node
1
, inputs potentials of the first and second buffer means
7
and
9
rise to the power supply potential, and output potentials of the first and second buffer means
7
and
9
rise from the ground potential (0V) to the power supply potential Vcc, thereby raising the potentials of the first and second capacitive elements
8
and
10
. The electrodes on one side of the first and second capacitive elements
8
and
10
are boosted from the ground potential (0V) to the power supply potential Vcc, so that the potentials of the first and second nodes
5
and
6
are raised from Vcc, which is the precharge potential, to two times Vcc by capacitive coupling of the first and second capacitive elements
8
and
10
.
The N-channel type MOS transistor
4
then conducts since its drain potential becomes 2Vcc; its gate potential becomes 2Vcc; and its source potential becomes Vcc−Vth
4
. Further, the charges at the first capacitive element
8
flow into the boosted potential node
2
through the N-channel type MOS transistor
4
and are stored thereat, so that the potential of the boosted potential node
2
is boosted to Vcc−Vth
4
+&agr;. The boosted portion &agr; of the potential at the boosted potential node
2
is determined from the capacitance shared between the capacitances of the first capacitive element
8
and the load capacitor
3
.
Then, at time T
1
, i.e., when the clock signal falls to the ground potential, the potentials of the first and second buffer means
7
and
9
also fall to the ground potential, so that the potentials of the first and second nodes
5
and
6
fall to Vcc by the capacitive coupling of the first and second capacitive elements
8
and
10
. The N-channel type MOS transistor
4
becomes nonconductive, because its drain potential equals Vcc; its gate potential equals Vcc; and its source potential equals Vcc−Vth
4
+&agr;. Hence, there is no charge flow from the boosted potential node
2
to the first node
5
.
Next, when the clock signal is raised again to the power supply potential Vcc at time T
2
, the outputs of the first and second buffer means
7
and
9
rise from the ground potential to the power supply potential Vcc, thereby (similar to above) raising the potentials of the first and second capacitive elements
8
and
10
, and boosting the potentials of the first and second nodes
5
and
6
to two times Vcc. Further, the N-channel type MOS transistor
4
becomes conductive, and the charges at the first capacitive element
8
flow into the boosted potential node
2
through the N-channel type MOS transistor
4
, thereby further raising the potential of the boosted potential node
2
. The potential of the boosted potential node
2
is thus boosted stepwise at every rise of the clock signal from the ground potential to the power supply potential, and the boosted potential of 2Vcc−Vth
4
is finally obtained at the boosted potential node
2
.
As shown in
FIG. 9
, since the N-channel type MOS transistor
4
, in which the negative potential Vbb is fed to the back gate, is used as the drive transistor, the substrate potential (potential of the p-well region
12
, i.e., the effective substrate potential) viewed from the source electrode (or the electrode connected to the boosted potential node
2
in this situation) is very deep, and the threshold voltage Vth
4
is large. Hence, the boosted potential Vpp obtained at the boosted potential node
2
cannot obtain a high potential.
Another type of a boosted potential generating circuit is shown in
FIGS. 10-12
, which is not affected from the threshold voltage Vth
4
, and hence is capable of rendering a higher boosted potential Vpp at the boosted potential node
2
. The boosted potential generating circuit of
FIG. 10
includes an N-channel type MOS transistor
4
with a structure capable of b

Affiliated with

Also associated with

Rating

Boosted potential generating circuit does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Boosted potential generating circuit, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Boosted potential generating circuit will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-2452295