Boosted high gain, very wide common mode range, self-biased...

Amplifiers – With semiconductor amplifying device – Including differential amplifier

Reexamination Certificate

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C330S257000

Reexamination Certificate

active

06469579

ABSTRACT:

FIELD
Embodiments of the present invention relate to analog circuits, and more particularly, to operational amplifiers.
BACKGROUND
Many prior art CMOS (Complementary-Metal-Oxide-Semiconductor) operational amplifiers rely upon external biasing in order to bias in the saturation region various FETs (Field-Effect-Transistor) that serve as current sources (or active loads) in the operational amplifiers. However, external biasing may be sensitive to process technology, supply voltage, and temperature. Furthermore, because the overall gain and output resistance of an operational amplifier may both be very high and difficult to accurately model, the output node voltages for zero differential input voltage is very difficult to predict. In general, these node voltages should be at or near V
cc
/2 for zero differential input voltage, where V
cc
is the supply voltage.
Other prior art operational amplifiers have utilized various methods of self-biasing with negative feedback, so that the output node voltages are nominally at V
cc
/2. However, for some of these prior art operational amplifiers, external biasing is not completely eliminated, and for others, some or all the FETs that serve as the current sources are biased in their linear region instead of their saturation region, resulting in reduced voltage gain. The present invention addresses these problems.


REFERENCES:
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patent: 5442318 (1995-08-01), Badyal et al.
patent: 5621374 (1997-04-01), Harkin
patent: 5748040 (1998-05-01), Leung
patent: 5789981 (1998-08-01), Singer et al.
patent: 6028480 (2000-02-01), Seevinck et al.
patent: 6064267 (2000-05-01), Lewyn
patent: 6150883 (2000-11-01), Ivanov
patent: 028932 (1981-05-01), None
Mel Bazes, “Two Novel Fully Complementary Self-Biased CMOS Differential Amplifiers”, 1991 IEEE, pp. 165-168.
John A. Fisher and Rudolf Koch, “A Highly Linear CMOS Buffer Amplifier”, IEEE Journal of Solid-State Circuits, vol. SC-22, No. 3, Jun. 1987, pp. 330-334.
Klaas Bult and Govert J.G.M. Geelen, “A Fast-Settling CMOS Op Amp for SC Circuits with 90-dB DC Gain”, IEEE Journal of Solid-State Circuits, vol. 25, No. 6, Dec. 1990, pp. 1379-1384.
Richard E. Vallee and Ezz I. E1-Masry, “A Very High-Frequency CMOS Complementary Folded Cascode Amplifier”, IEEE Journal of Solid-State Circuits, vol. 29, No. 2, Feb. 1994, pp. 130-133.
Peter J. Holzmann et al., “A Low-Offset Low-Voltage CMOS OP AMP With Rail-To-Rail Input and Output Ranges”, 1996 IEEE International Symposium On Circuits and Systems, May 12, 1996, pp. 179-182.

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