Boosted clock circuit for semiconductor memory

Details Boosted clock circuit for semiconductor memory Boosted clock circuit for semiconductor memory

2008-05-20

2008-05-20

Pham, Ly Duy (Department: 2827)

Static information storage and retrieval

Addressing

Sync/clocking

C365S189090, C365S189110

Reexamination Certificate

active

11492636

ABSTRACT:
A memory component includes at least one memory bank array, a DQ region, a clock tree, and a voltage generator. The memory component is configured in a semiconductor wafer. The at least one memory bank array is configured such that data is read out of it during a read operation. The clock tree is coupled to the DQ region and is configured for driving data during the read operation. The voltage generator is coupled to at least some components of the clock tree in order to provide at least some of the components of the clock tree with an increased voltage.

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patent: 2003/0037271 (2003-02-01), Liu et al.
patent: 2000035831 (2000-02-01), None

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