Boost word-line clock and decoder-driver circuits in semiconduct

Electrical transmission or interconnection systems – Nonlinear reactor systems – Parametrons

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307269, 307481, 307482, 307463, 365230, H03K 19096

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046789413

ABSTRACT:
A CMOS boost word-line clock and decoder-driver circuit which can be used for CMOS DRAM's with substrate bias in addition to VDD supply. A boost word-line clock circuit including simple CMOS inverters is used for the word-line boost and the possible voltage overshoot, which usually occurs because of capacitor two-way boost, can be completely eliminated. Also, the circuit can be triggered by a single clock. A high performance decoder circuit is provided in combination with the aforesaid CMOS boost word-line clock circuit, such decoder using NMOS pass-gate in the decoder driver and providing fast word-line boosting. The timing between the decoder and the word-line clock activation is not crucial.

REFERENCES:
patent: 3778784 (1973-12-01), Karp et al.
patent: 3801831 (1974-04-01), Dame
patent: 3852625 (1974-12-01), Kubo
patent: 3943377 (1976-03-01), Suzuki
patent: 3947829 (1976-03-01), Suzuki
patent: 3982138 (1976-09-01), Luisi et al.
patent: 3999081 (1976-12-01), Nakajima
patent: 4000412 (1976-12-01), Rosenthal et al.
patent: 4029973 (1977-06-01), Kobayashi et al.
patent: 4045691 (1977-08-01), Asano
patent: 4061929 (1977-12-01), Asano
patent: 4145622 (1979-03-01), Hofmann et al.
patent: 4156938 (1979-05-01), Proebsting et al.
patent: 4194130 (1980-03-01), Moench
patent: 4200917 (1980-04-01), Moench
patent: 4216390 (1980-08-01), Stewart
patent: 4259731 (1981-03-01), Moench
patent: 4264828 (1981-04-01), Perlegos et al.
patent: 4309629 (1982-01-01), Kamuro
patent: 4330719 (1982-05-01), Nagami
patent: 4344005 (1982-08-01), Stewart
patent: 4429374 (1984-01-01), Tanimura
patent: 4433257 (1984-02-01), Kinoshita
patent: 4496850 (1985-01-01), Takemae et al.
patent: 4514829 (1985-04-01), Chao
patent: 4571503 (1986-02-01), Tobita
Aipperspach et al., "Bootstrap Voltage Generator for Dynamic RAM Array", IBM TDB vol. 25, No. 7A, pp. 3234-3235; 12/1982.
Tien, "Bit Line Selection Circuit for Programming Level Voltages in an Electrically Alterable Read-Only Storage", IBM TDB; vol. 23, No. 10, pp. 4574-4576; 3/1981.
IBM Technical Disclosure Bulletin, vol. 25, No. 4, Sep. 1982, pp. 2135-2136, L. M. Terman, "CMOS Decoder Circuit".
IBM Technical Disclosure Bulletin, vol. 18, No. 12, May 1976, pp. 3955-3956, G. H. Parikh, "High-Speed FET Decoder".

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