Boost doubler circuit

Miscellaneous active electrical nonlinear devices – circuits – and – Specific identifiable device – circuit – or system – With specific source of supply or bias voltage

Reexamination Certificate

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Details

C363S060000

Reexamination Certificate

active

06522192

ABSTRACT:

BACKGROUND
1. Field of the Invention
The present invention relates to switched power supplies.
2. Description of Related Art
Voltage doubler circuits are known. Also known are switched power supplies, including “boost” circuits used to generate a voltage higher than a supply voltage and “buck” circuits used to generate a lower voltage.
FIG. 1
illustrates a simple boost circuit that is commonly used to generated a voltage that is greater than the supply voltage Vcc. An inductor L
1
is coupled at node
1
of the circuit to a switch SW
1
and through the switch to ground. Also coupled to node
1
is a Schottky diode D
1
. A capacitor C
2
is coupled to the output of D
1
, at which the output voltage VPA of the circuit is produced. The output voltage is applied to a resistive load RL.
In operation, when SW
1
is on, a current builds up in L
1
. When SW
1
is then turned off in accordance with, a clock signal T
1
, the voltage at node
1
will rise until it is caught by (exceeds the forward conduction voltage of) the Schottky diode D
1
, and the stored energy in the inductor is transferred to C
2
. For a given load RL, the voltage VPA can be set by the on-time to off-time ratio of the switch SW
1
. Typically, some form of voltage comparator (not shown) is used to drive a pulse width modulator (not shown) to regulate the voltage VPA. Since energy transfer is accomplished with a reactive device, the efficiency of this type of circuit can be quite high (85% or more) and is limited only by the parasitic resistances, the core loss of the inductor, and the diode drop. Using an additional switch across D
1
can further reduce the diode drop loss. The inductor L
1
, however, can be quite large if a large boltage boost is desired, because the energy required to be stored is correspondingly large.
FIG. 2
illustrates a simple voltage doubler. A capacitor C
1
has one plate thereof coupled at node
1
of the circuit to a switch SW
1
and through the switch to Vcc. Also coupled to node
1
is a Schottky diode D
1
. A capacitor C
2
is coupled to the output of D
1
, at which the output voltage VPA of the circuit is produced. The output voltage is applied to a resistive load RL. The other plate of the capacitor C
1
is coupled through a switch SW
2
to ground and through a switch SW
3
to Vcc. Control of switch SW
1
and SW
2
is ganged.
In operation, SW
1
and SW
2
are turned on charging C
1
to Vcc. SW
1
and SW
2
are then turned off and SW
3
turned on. Since node
1
is Vcc above node
2
, when node
2
is switched to Vcc, node
1
will rise to 2 Vcc. This continuing action will cause VPA to rise to 2 Vcc minus the drop across D
1
, assuming the capacitors C
1
and C
2
are sufficiently large. A switch can be used in place of D
1
to improve efficiency. This circuit can provide a single voltage out at good efficiency; however, any attempt to regulate VPA will result in a loss of efficiency equivalent to adding a linear regulator between C
2
and VPA. Also, as shown in
FIG. 3
, this circuit requires that clocks T
1
and T
2
be non-overlapping clocks to avoid major loss of efficiency.
What is needed, then, is a voltage regulator circuit, having at least one of a boost mode of operation and buck mode of operation, that overcomes the foregoing disadvantages.
SUMMARY OF THE INVENTION
The present invention, generally speaking, provides a circuit that combines the features of a voltage doubler and a boost regulator to achieve a small and efficient voltage boost regulator. A capacitor is used to provide a primary voltage boost effect. An inductor is used to provide further regulation, either further boost or buck. Instead of requiring non-overlapping clock signals, the relative timing and overlap of the clock signals determines the regulation achieved. The inductor can be made significantly smaller than in comparable boost circuits, facilitating size reduction.


REFERENCES:
patent: 3878449 (1975-04-01), Wilhelmi et al.
patent: 4403279 (1983-09-01), Hirsch
patent: 4691271 (1987-09-01), Rosenbaum et al.
patent: 4994953 (1991-02-01), Haak
patent: 5345376 (1994-09-01), Farhad
patent: 5350997 (1994-09-01), Ghotbi et al.
patent: 5565761 (1996-10-01), Hwang
patent: 5774348 (1998-06-01), Druce et al.
patent: 6028418 (2000-02-01), Jovanovic
patent: 6043610 (2000-03-01), Buell
patent: 6201717 (2001-03-01), Grant
patent: 0 700 146 (1996-03-01), None
patent: 07123702 (1995-12-01), None

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