Boost clock circuit for driving redundant wordlines and sample w

Details Boost clock circuit for driving redundant wordlines and sample w Boost clock circuit for driving redundant wordlines and sample w

1989-01-13

1990-05-01

Miller, Stanley D.

Electrical transmission or interconnection systems

Nonlinear reactor systems

Parametrons

307481, 328104, 328137, 328154, H03K 19096, H03K 513

Patent

active

049221280

ABSTRACT:
A boost clock signal generator which provides a boost clock signal from a pair of phase clocks. A pair of differentially-connected FET transistors which generate a boost clock signal. The transistors have drain connections connected to each of two clock signals, and commonly connected sources which form an output terminal for the boost clock signal. A series pass FET transistor is connected with each gate of the differential transistors for maintaining the gate at a floating voltage potential. A pair of capacitive elements couple the drain of each pair of differentially-connected FET transistors to the gate of an opposite transistor. A first and second logic circuit are connected to the series pass FET transistors for enabling one or the other of the differnetially-connected FET transistors into conduction. The pair of capacitive coupling elements coupling the drain of each pair of differentially-connected FET transistors to the gate of an opposite transistor increase switching speed of the clock signal generator.

REFERENCES:
patent: 2867723 (1959-01-01), Spaulding
patent: 3654394 (1972-04-01), Gordon
patent: 3969634 (1976-07-01), Machettii et al.
patent: 4490626 (1984-12-01), Carlson
patent: 4494018 (1985-01-01), Clemen et al.
patent: 4562365 (1985-12-01), Redfield
patent: 4599528 (1986-07-01), Redfield
patent: 4639614 (1987-01-01), Basile
patent: 4794275 (1988-12-01), Traa

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