Miscellaneous active electrical nonlinear devices – circuits – and – Specific identifiable device – circuit – or system – With specific source of supply or bias voltage
Reexamination Certificate
2000-06-30
2003-11-18
Cunningham, Terry D. (Department: 2816)
Miscellaneous active electrical nonlinear devices, circuits, and
Specific identifiable device, circuit, or system
With specific source of supply or bias voltage
C327S537000
Reexamination Certificate
active
06650172
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates in general to a boost circuit, and more particularly to a boost circuit which is designed in such a way as to reduce the power source current when activating the boost circuit.
2. Description of the Related Art
A configuration of a prior art example of a boost circuit is shown in
FIG. 15 and a
timing chart thereof is shown in FIG.
16
.
In this circuit, boosting operation is terminated by setting CTL at a low level. Since output node P
1
of a NAND
151
which has received that input is held at a high level irrespective of the level of the input from CLK, the boosting operation is not carried out in each of pumping circuits
158
A to
158
H.
On the other hand, CTL is set to a high level to allow the boosting operation. A clock signal which has been inputted to the CLK is inverted to be outputted from the NAND
151
. The pumping circuits
158
A to
158
H, each of which has received the inverted clock signal, start the boosting operation at the same time.
Some semiconductor devices receive an external electric wave to activate the internal power source on the basis of the electric wave thus received. One example is the noncontact IC card, for which an increase of demand is expected. In such device there arises the problem that the power source voltage is reduced due to the increase of the power source current when starting the boosting operation.
In this connection,
FIG. 19
is a graphical representation showing the simulation result of this circuit. In the figure, reference numeral
251
designates a waveform of a boosted voltage (VPP) and reference numeral
252
designates a waveform of a power source current (IDD). The boosted voltage of this circuit is 17.0 V and the peak current thereof is 842 &mgr;A.
Next, a circuit diagram disclosed in Japanese Patent Application Laid-open No. Hei 268294 is shown in
FIG. 17 and a
timing chart thereof is shown in FIG.
18
.
In this circuit, a clock signal is inputted from a CLK and pumping circuits
204
A to
204
H each of which has received the clock signal thus inputted thereto start the boosting operation. A point of difference between this circuit and that circuit shown in
FIG. 15
is that the voltage which has been boosted in the pumping circuit
204
A in the previous stage is used as the power source of a level shifter
201
B which is the constituent element of the pumping circuit
204
B in the next stage. Likewise, the voltages which have been respectively boosted in the pumping circuits in the previous stages are used as the power sources of level shifters
201
C to
201
H, respectively.
However, in this boost circuit, the level shifters are used in the clock driver. As a result, since the output of each of the level shifters becomes equal to or lower than 0 V when starting the boosting operation, the switching device provided between the pumping circuits needs to be comprised of an N-channel enhancement MOS transistor having Vt which is larger than 0 V.
Therefore, the voltage which is transferred to the next stage during the boosting operation is expressed by the following expression:
VDD−Vt
(1)
and hence the transferred voltage is lost by Vt as compared with the prior art example.
Since the loss of voltage in the transferred voltage occurs in each of the stages of the pumping circuits
204
A to
204
H, there arises the problem that it takes a lot of time to boost the voltage.
In this connection,
FIG. 20
is a graphical representation showing the simulation result of this circuit which has the pumping circuits of four stages. In the figure, reference numeral
261
designates a waveform of the boosting voltage (VPP), and reference numeral
262
designates a waveform of the power source current (IDD). The boosting voltage of this circuit is 5.3 V and the peak current thereof is equal to or larger than 10 mA.
In addition,
FIG. 21
is a graphical representation showing the simulation result of this circuit which has the pumping circuits of eight stages. In the figure, reference numeral
271
designates a waveform of the boosted voltage (VPP) and reference numeral
272
designates a waveform of the power source current (IDD).
SUMMARY OF THE INVENTION
In light of the foregoing, the present invention has been made in order to solve the above-mentioned problems associated with the prior art, and it is therefore an object of the present invention to provide a novel boost circuit which is designed in such a way as to reduce the consumed current when activating the boost circuit.
In order to attain the above-mentioned object, the present invention adopts the following technical configurations.
The first aspect of the present invention provides a boost circuit comprising: a plurality of charge pump circuit stages, each charge pump circuit stage having a V
i
input, a clock input, and a V
o
output, each circuit stage providing a voltage at the V
o
output which is higher than a voltage at the V
i
input, the V
i
input of a first of the circuit stages being connected to a power supply voltage, each of the plurality of circuit stages other than the first stage having its V
i
input connected to the V
o
output of an immediately preceding circuit stage. During a startup condition, each of the clock signals transitions from an inactive state to a reciprocating state, the transition of each of the clock signals being delayed by at least one clock cycle with respect to each transition of the clock signal supplied to each preceding stage.
In addition, the second aspect of the present invention provides a boost circuit comprising a first multi-stage charge pump circuit receiving a first clock signal at a first level and an input, the first multi-stage charge pump circuit producing a first output voltage having a higher voltage level than the input voltage, a level shifter receiving the first output voltage, the level shifter having a level shifter clock input and a shifted clock output, the level shifter producing a second clock signal at the shifted clock output having a predetermined higher voltage level than an input clock signal received at the level shifter clock input, and a second multi-stage charge pump circuit receiving the first output voltage and the second clock signal, the second multi-stage charge pump circuit producing a second output voltage having a higher voltage level than the first output voltage. Each stage of the second multi-stage charge pump circuit has a clock input which receives a clock signal at the predetermined higher voltage when the multi-stage charge pump reached steady state.
According to the present invention, the charge pump circuits are prevented from starting the boosting operation at the same time when activating the boost circuit.
As a result, there is obtained the effect that it is possible to reduce the power source current consumption when starting the boosting operation.
REFERENCES:
patent: 4935644 (1990-06-01), Tsujimoto
patent: 5216588 (1993-06-01), Bajwa et al.
patent: 5301097 (1994-04-01), McDaniel
patent: 5489870 (1996-02-01), Arakawa
patent: 5642073 (1997-06-01), Manning
patent: 5734290 (1998-03-01), Chang et al.
patent: 5821805 (1998-10-01), Jinbo
patent: 5831844 (1998-11-01), Sudo
patent: 5889428 (1999-03-01), Young
patent: 5940284 (1999-08-01), Troutman
patent: 4-268294 (1992-09-01), None
patent: A 7-244990 (1995-09-01), None
patent: A 8-149799 (1996-06-01), None
patent: A 10-304653 (1998-11-01), None
patent: A 11-164545 (1999-06-01), None
patent: 99/03192 (1999-01-01), None
Cunningham Terry D.
NEC Electronics Corporation
Young & Thompson
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