Miscellaneous active electrical nonlinear devices – circuits – and – Specific identifiable device – circuit – or system – With specific source of supply or bias voltage
Reexamination Certificate
2000-03-22
2001-11-20
Cunningham, Terry D. (Department: 2816)
Miscellaneous active electrical nonlinear devices, circuits, and
Specific identifiable device, circuit, or system
With specific source of supply or bias voltage
C356S136000, C356S136000
Reexamination Certificate
active
06320455
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a boost circuit of a semiconductor integrated circuit, and in particular to a boost circuit capable of outputting a boost voltage decreased in dispersion by simulatively detecting outputs of boost circuit units and controlling the number of circuit units to be activated among a plurality of boost circuit units connected in parallel.
2. Description of the Related Art
Recently in a semiconductor memory device such as a flash memory, reduction of the current consumption of a whole memory chip is demanded as the power supply voltage required to actuate the semiconductor memory device is lowered. Therefore, a voltage which is needed within the memory and which is higher than the power supply voltage needs to be generated by raising the power supply voltage to a desired high voltage within the chip. For such a purpose, a boost circuit is used.
FIG. 1
is a block diagram showing a conventional boost circuit. In this boost circuit, a boost input voltage B
BOOST
is inverted by an inverter
40
. The inverted voltage is input to a transistor
41
, and output as an amplified voltage V
BOOST
via capacitance
42
. The transistor
41
is controlled at its gate by a level shifter (L/S)
43
. On the basis of the input voltage B
BOOST
and the output voltage V
BOOST
, the L/S
43
controls the gate voltage of the transistor
41
.
However, this conventional boost circuit has a problem that the output voltage is largely varied due to variations in the power supply voltage and external temperature and dispersions in process factors of the chip.
Heretofore, therefore, as shown
FIG. 2
, there has been proposed such a boost circuit that the boost circuit shown in
FIG. 1
is used as each of boost circuit units
32
and
33
and the boost circuit units
32
and
33
, are connected in parallel between an input terminal
31
and an output terminal
38
.
In this conventional boost circuit, the input terminal
31
is input with a boost input voltage ATDBST
2
. Between the input terminal
31
and the boost circuit unit
32
, an inverter
34
is connected. Between the input terminal
31
and the boost circuit unit
33
, a NAND circuit
35
is connected. A power supply voltage detection circuit
37
is connected to the other input terminal of the NAND circuit
35
. As a result, the boost input voltage ATDBST
2
and an output signal of the power supply voltage detection circuit
37
are input to the NAND circuit
35
. A logical product of them is input to the boost circuit unit
33
. The power supply voltage detection circuit
37
outputs a “high” signal when a power supply voltage Vcc is lower than a predetermined voltage V
LIMIT
, and outputs a “low” signal when the power supply voltage Vcc is equal to or higher than V
LIMIT
.
Furthermore, between the output terminal
38
and a ground terminal, a capacitor
36
having capacitance C
L
is connected. And an amplified voltage V
BOOST
is output from the output terminal
38
.
Operation of this conventional boost circuit will now be described. The power supply voltage detection circuit
37
outputs a “high” signal when a power supply voltage Vcc is lower than a predetermined voltage V
LIMIT
. Via the NAND circuit
35
, the boost input voltage ATDBST
2
is input to the boost circuit unit
33
as well. The boost circuit unit
33
is thus activated. In this case, the boost circuit operates by using two circuit units, i.e., the boost circuit unit
32
and the boost circuit unit
33
.
The power supply voltage detection circuit
37
outputs a “low” signal when the power supply voltage Vcc is equal to or higher than a predetermined voltage V
LIMIT
. The boost input voltage ADBST
2
is not input to the boost circuit unit
33
. Accordingly, the boost circuit unit
33
ceases its operation. In this case, the boost circuit operates with one boost circuit unit, i.e., the boost circuit unit
32
.
By controlling the number of activated boost circuit units to be activated according to the variation of the power supply voltage, therefore, the variation of the output of the boost circuit can be suppressed.
In the above-described conventional boost circuit, however, only the variation of the power supply voltage is detected. Although it is possible to prevent the variation of the boost circuit output caused by the variation of the power supply voltage, therefore, there has been a problem that variation of the boost voltage itself caused by dispersion of the process condition and the variation of the external temperature cannot be suppressed.
SUMMARY OF THE INVENTION
An object of the present invention is to provide a boost circuit capable of suppressing the dispersion of the boost voltage caused by the dispersion of the process condition and the variation of the external temperature besides the variation of the power supply voltage Vcc.
According to the present invention, a boost circuit comprises: a main part of the boost circuit including a plurality of (n) boost circuit units connected in parallel; a boost voltage detection section including a dummy boost circuit unit having the same configuration as the boost circuit units of the main part of the boost circuit, and a voltage detection circuit for detecting an output voltage of the dummy boost circuit unit; and a selection circuit for selecting the number of boost circuit units to be activated in the main part of the boost circuit, based on a result of detection of the boost voltage detection section.
The voltage detection circuit may be adapted to compare the output voltage of the dummy boost circuit unit with a specific voltage V
LIMIT
and output a “high” or “low” test signal.
Furthermore, the min part of the boost circuit may be adapted to include an input terminal for inputting a signal to the boost circuit units connected in parallel; and an output terminal for outputting a signal supplied from the boost circuit units connected in parallel, and the selection circuit may be adapted to include an inverter connected between the input terminal and a first boost circuit unit; (n−1) NAND circuits respectively connected between the input terminal and second to nth boost circuit units; and a circuit for inputting the test signal to the NAND circuits.
In this case, the boost circuit may have such a configuration that the main part of the boost circuit has two boost circuit units connected in parallel, and the specific voltage V
LIMIT
is one in number.
Or the boost circuit may have such a configuration that the main part of the boost circuit has m (where m is a natural number of at least 3) boost circuit units connected in parallel, (m−1) values of the voltage V
LIMIT
are set, and (m−1) test signals depending on the (m−1) values of the specific voltage V
LIMIT
are input to (m−1) boost circuit units, respectively.
In the present invention, a dummy boost circuit unit having the same configuration as the boost circuit units of the main part of the boost circuit is provided and the number of activated boost circuit units of the boost circuit is controlled by detecting the boost voltage of the dummy boost circuit unit. Accordingly, the boost voltage output from the main part of the boost circuit can be controlled so as to be within a fixed narrow width. As a result, it is possible to absorb not only the variation of the power supply voltage but also the dispersion of the process condition and the variation of the external temperature. The dispersion of the boost voltage can thus be suppressed. In addition, it is possible to reduce wasteful current consumption by limiting the number of activated boost circuit units when the boost output is high.
REFERENCES:
patent: 6141262 (2000-10-01), Sudo
patent: 4-313889 (1992-11-01), None
patent: 7-326194 (1995-12-01), None
patent: 9-172371 (1997-06-01), None
patent: 9-265794 (1997-10-01), None
patent: 10-050088 (1998-02-01), None
patent: 10-104282 (1998-04-01), None
Cunningham Terry D.
NEC Corporation
Tra Quani
Young & Thompson
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