Boolean logic tree reduction circuit

Details Boolean logic tree reduction circuit Boolean logic tree reduction circuit

2006-02-21

2006-02-21

Nguyen, Linh Van (Department: 2819)

Coded data generation or conversion

Digital code to digital code converters

Tree structure

C341S051000

Reexamination Certificate

active

07002493

ABSTRACT:
A method and apparatus are provided for performing a Boolean logic tree function on all bits of a multiple-bit binary input data word having a plurality of bit positions. Each bit has one of first and second complementary logic states. A modified data word is formed by packing all the bits of the input data word having the first logic state into a first contiguous set of bit positions in the modified data word and all the bits of the input data word having the second logic state into a second contiguous set of the bit positions in the modified data word. The number of bit positions in the first and second sets is greater than or equal to zero. A result of the Boolean logic tree function is generated based on a pattern of the first and second logic states in the modified data word.

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