Bonding pads for semiconductor devices

Details Bonding pads for semiconductor devices Bonding pads for semiconductor devices

1984-07-05

1985-04-30

Tufariello, Thomas

Chemistry: electrical and wave energy

Processes and products

204DIG9, C25D 502

Patent

active

045142653

ABSTRACT:
An improved process for electroplating bonding pads, such as of gold, onto semiconductor devices is disclosed. Upon electrically connecting a masked semiconductor body and a suitable anode to the negative and positive terminals respectively of a power supply and submerging the wafer and anode into a suitable electrolyte, a modulated, rather than direct, current is applied to the electrolyte. A low stress, fine grain bonding pad layer is provided and, unexpectedly, non-planarities in the semiconductor body surface having a depth of about 1-3 microns can be substantially planarized when the thickness of the layer deposited is about 6-8 microns or more.

REFERENCES:
patent: 2451341 (1948-10-01), Jernstedt
patent: 3738927 (1973-06-01), Miller
patent: 4082622 (1978-04-01), Gebauer
patent: 4347486 (1982-08-01), Botez
patent: 4465564 (1984-08-01), Fletcher
IBM Technical Disclosure Bulletin, vol. 16, No. 3, Aug. 1973, pp. 979, 980.
F. H. Reid et al., "Gold Plating Technology", Electrochemical Publications Limited, (1974).
Norman M. Osero, "Pulse Plating", Metal Finishing Guidebook, (1982).

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