Bonding pad structure for integrated circuit (III)

Details Bonding pad structure for integrated circuit (III) Bonding pad structure for integrated circuit (III)

1998-03-13

1999-10-05

Thomas, Tom

Active solid-state devices (e.g., transistors, solid-state diode

Combined with electrical contact or lead

Of specified material other than unalloyed aluminum

257758, 257781, 257773, 438612, 438614, H01L 2348

Patent

active

059629193

ABSTRACT:
A bonding pad structure in accordance with the present invention is formed on a semiconductor substrate. The bonding pad structure comprises a buffer layer, a planarization layer, a conducting pad, and a passivation layer. The buffer layer is formed over the semiconductor substrate, and the planarization layer is thereafter formed on the buffer layer. The buffer layer is patterned and etched to shape a plurality of contact holes. The conducting pad is formed on the planarization layer and filled in the contact holes in order to mechanically interlock with the planarization layer. The passivation layer overlies peripherals of the conducting pad forming an overhang region therebetween. Moreover, the width of a portion of the overhang region close to a drawing direction may be enlarged so that the adhesion between the conducting pad and the passivation layer can be increased.

REFERENCES:
patent: 4060828 (1977-11-01), Satonaka
patent: 5248903 (1993-09-01), Heim
patent: 5372969 (1994-12-01), Moslehi
patent: 5463245 (1995-10-01), Hiruta
patent: 5707894 (1998-01-01), Hsiao
patent: 5736791 (1998-04-01), Fujiki et al.

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