Active solid-state devices (e.g. – transistors – solid-state diode – Combined with electrical contact or lead – Of specified material other than unalloyed aluminum
Reexamination Certificate
1999-05-06
2001-05-22
Potter, Roy (Department: 2822)
Active solid-state devices (e.g., transistors, solid-state diode
Combined with electrical contact or lead
Of specified material other than unalloyed aluminum
C257S774000, C257S786000
Reexamination Certificate
active
06236114
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor device. More particularly, the present invention relates to a bonding pad structure.
2. Description of the Related Art
Typically, the structure of a bonding pad includes multiple layers of dielectric layers and metal layers. The adhesion of the dielectric layers and the metal layers is poor and compressive mechanical stress acts on the dielectric layer while bonding wires are bonded to bonding pads by thermocompression, so that the bonding pads often peel off and the dielectric layers often crack. Hence, the package yield and the reliability are relatively low.
In order to overcome the problem caused by the formation of the bonding wires, several bonding pad structures referred to in T. W. U.S. Pat. No. 248,340, T. W. U.S. Pat. No. 329,984 and U.S. Pat. No. 4,984,061 are developed. The ideas of those bonding pad structures are the same, that is, forming holes in the dielectric layers. By using the bonding pad structures, the adhesion of the dielectric layers and the metal layers can be improved. At the same time, the stress induced while the wire bonding step is performed can be released to the substrate via those holes. Therefore, the bonding pads peeling off can be suppressed. However, when the hole size shrinks in the next generation of technology, the efficacy of the structures mentioned above is minimal, since contact area of the hole decreases.
SUMMARY OF THE INVENTION
The invention provides a bonding pad. By using the invention, the adhesion of the dielectric layers and the metal layers can be greatly improved and compressive mechanical stress can be uniformly released by the substrate even if the wire width of the integrated circuit is reduced to the sub-micron level.
To achieve these and other advantages and in accordance with the purpose of the invention, as embodied and broadly described herein, the invention provides a bonding pad located on a substrate having integrated circuits formed therein. A dielectric layer having several trench structures formed therein is formed over the substrate, and each trench structure has several trenches radially arranged in the dielectric layer. A conductive layer is formed on the dielectric layer and fills the trenches, and the conductive layer is electrically coupled to the integrated circuits in the substrate through the trenches, respectively.
The invention provides a bonding pad located on a substrate having integrated circuits formed therein. Alternating dielectric layers with conductive layers are formed over the substrate, and each of the dielectric layers has several trench structures formed therein. Each of the trench structures has several trenches radially arranged in the dielectric layers and the trench structures in adjacent dielectric layers are staggered with respect to each other. The dielectric layers are electrically coupled to each other through the trenches and one of the dielectric layers above the substrate is electrically coupled to the substrate through the trenches in this particular dielectric layer.
The invention provides a bonding pad located on a substrate having integrated circuits formed therein. Alternating dielectric layers with conductive layers are formed over the substrate, and each of the dielectric layers has several trench structures formed therein. Each of the trench structures has four trenches arranged in a tetraskelion in the dielectric layers and the trench structures in adjacent dielectric layers are staggered with respect to each other. The dielectric layers are electrically coupled to each other through the trenches and one of the dielectric layers above the substrate is electrically coupled to the substrate through the trenches in this particular dielectric layer. Since the trench structure can provide a relatively large contact area, the adhesion of the dielectric layers and the metal layers can be greatly improved. Additionally, the compressive mechanical stress from any direction, which is induced while the wire bonding step is performed, can be uniformly released to the substrate through the trench structures in the bonding pad even if the wire width of the integrated circuit is reduced to the sub-micron level.
It is to be understood that both the foregoing general description and the following detailed description are exemplary, and are intended to provide further explanation of the invention as claimed.
REFERENCES:
patent: 5923088 (1999-07-01), Shiue et al.
Fu Huan-Sung
Huang Min-San
Wang Ling-Sung
Wang Yong-Kang
Wu Jyh-Ren
Huang Jiawei
J. C. Patents
Potter Roy
Taiwan Semiconductor Manufacturing Co. Ltd.
LandOfFree
Bonding pad structure does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Bonding pad structure, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Bonding pad structure will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2542330