Bonding pad on a semiconductor chip

Details Bonding pad on a semiconductor chip Bonding pad on a semiconductor chip

2001-03-08

2002-05-14

Flynn, Nathan (Department: 2826)

Active solid-state devices (e.g., transistors, solid-state diode

Combined with electrical contact or lead

Of specified material other than unalloyed aluminum

C257S750000, C257S632000, C257S635000, C257S644000

Reexamination Certificate

active

06388326

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor chip, and more particularly, to a bonding pad on a semiconductor chip.
2. Description of the Prior Art
In a semiconductor process, when MOS transistors are formed on a semiconductor chip, the MOS transistors are connected by using multiple metallic interconnects. Contact of the metallic interconnects and the MOS transistors is avoided by depositing dielectric layers with a lower dielectric constant. This also reduces induced capacitance between them thus increasing the speed of signal transmission. When forming the last layer of metallic interconnects, a bonding pad will be formed in a predetermined area on the last dielectric layer as an interconnection area in a follow-up packaging process.
Please refer to FIG.
1
.
FIG. 1
is a perspective view of the structure of a bonding pad
14
of a prior art semiconductor wafer
10
. After forming the last dielectric layer
12
on the semiconductor wafer
10
, the last layer of metallic interconnects is formed, and a metallic layer is formed as the bonding pad
14
in a predetermined area on the dielectric layer
12
. After an error-free electrical test is performed, the semiconductor wafer
10
is then sectioned into individual chips for performing a following packaging process. If the dielectric constant of the dielectric layer
12
is too high, the speed of signal transmission between the dielectric layers
12
will be reduced. Therefore, the dielectric layer
12
is made of fluoride silicate glass (FSG) in the prior art with a low dielectric constant.
Please refer to FIG.
2
.
FIG. 2
is a perspective view of the bonding pad
14
on a chip
15
connected to a metallic wire
18
. When performing a wire bonding process, one side of the chip
15
is first fixed onto a baseplate
16
and one end of the metallic wire
18
is heated to form a metallic ball
17
. This allows bonding of the metallic wire
18
to the bonding pad
14
. Next, the other end of the metallic wire
18
is dragged to and linked to a predetermined area of the baseplate
16
so that electronic signals of the chip
15
can be transmitted to external components. The dielectric layer
12
below the bonding pad
14
is made of flouride silicate glass (FSG) with a lower degree of hardness. Therefore, when the metallic wire
18
is dragged across the surface of the baseplate
16
, or when the chip
15
is washed by performing a supersonic vibration process, the metallic ball
17
, bonding pad
14
and part of the dielectric layer
12
are peeled off from the surface of the chip
15
. This causes damage to the chip
15
and reduces reliability of packaging.
SUMMARY OF THE INVENTION
It is therefore a primary objective of the present invention to provide a bonding pad on a semiconductor chip to solve the above mentioned problem.
In a preferred embodiment, the present invention provides a bonding pad on a semiconductor chip, the bonding pad being used to electrically connect an integrated circuit in the semiconductor chip with an external circuit. The semiconductor chip comprises a first dielectric layer positioned in a predetermined area on the surface of the semiconductor chip, a second dielectric layer positioned on the surface of the semiconductor chip outside the predetermined area wherein the first dielectric layer is harder than the second dielectric layer, and a bonding pad positioned on the first dielectric layer for electrically connecting an integrated circuit (IC) in the semiconductor chip with an external circuit.
It is an advantage of the present invention that by using a harder first dielectric layer, the bonding pad can be firmly bonded to the surface of the semiconductor chip without peeling. Since the dielectric constant of the second dielectric layer is lower in the present invention, signal transmission speeds are not affected.
This and other objectives of the present invention will no doubt become obvious to those of ordinary skill in the art after having read the following detailed description of the preferred embodiment which is illustrated in the various figures and drawings.


REFERENCES:
patent: 5100503 (1992-03-01), Allman et al.
patent: 5235212 (1993-08-01), Shimizu et al.
patent: 5795495 (1998-08-01), Meikle
patent: 5814893 (1998-09-01), Hsu et al.
patent: 6001733 (1999-12-01), Huang et al.
patent: 6086777 (2000-07-01), Cheng et al.
patent: 6232238 (2001-05-01), Chang et al.
patent: 6317974 (2001-11-01), Fjelstad
Streetman, “Solid State Electronic Devices,” 1990, Prentice-Hall, 3rd edition, p. 340-341.*
Wolf and Tauber, “Silicon Processing for the VLSI Era, vol. 1: Process Technology,” 1986, Lattice Press, p. 331-334.

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