Bonding pad and method for manufacturing it

Active solid-state devices (e.g. – transistors – solid-state diode – Combined with electrical contact or lead

Reexamination Certificate

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C257S779000, C257S781000, C257S782000, C257S784000, C257S786000

Reexamination Certificate

active

06426555

ABSTRACT:

FIELD OF THE INVENTION
The invention relates to the general field of integrated circuit manufacture with particular reference to forming bonding pads.
BACKGROUND OF THE INVENTION
Bonding pads, where connection is made between integrated circuits and the outside world, come in a variety of designs. A typical straightforward design of the prior art is illustrated in FIG.
1
. Damascene conductor
14
was previously embedded in the upper surface of dielectric layer
14
and then covered with a second (usually a passivating) layer
11
. Via hole
13
was then etched in
11
, to expose a portion of
14
, and aluminum bonding pad
12
was deposited and patterned so that it filled via hole
13
and overlapped its edges somewhat.
FIG. 2
is a plan view of this structure, with
FIG. 1
being a section taken at
1

1
of FIG.
2
.
While this type of design is easy to fabricate, it has the disadvantage that it is also associated with both a large area pad as well as a large underlying damascene area. This results in a large parasitic capacitance.
One approach to insulating the underlying metal from the bonding pad has been described by Heim in U.S. Pat. No. 5284,797. Heim's structure is shown in FIG.
3
. The structure of the underlying damascene conductor
14
is seen to be the same as in the structure of
FIG. 1
, but, instead of making contact all over its surface, via hole communication is confined to the outer edges of bonding. pad
33
. In this way pressure on pad
33
is not transmitted directly to the underlying conductor
14
but is buffered, at least to some extent, by the intervening dielectric layer
11
.
FIG. 4
is a plan view of the structure with
FIG. 3
being a cross-section taken at
3

3
.
Other references of interest include Shiue et al. (U.S. Pat. No. 5,700,735) who show a bonding pad with via plugs connecting between the first and second metal pads, Freeman, Jr et al. (U.S. Pat. No. 5,149,674 who describe a multi-layer bonding pad, and Hsue et al. (U.S. Pat. No. 5,661,081) who teach a bonding pad optimized to prevent peeling. Peeling prevention is also the main feature of the design by Ming-Tsung et al. (U.S. Pat. No. 5,834,365) who disclose a bond pad with strips/irregular surface.
SUMMARY OF THE INVENTION
It has been in object of the present invention to provide a bonding pad that protects the damascene conductor from damage during electrical probing and wire bonding.
A further object of the invention has been to provide a bond pad structure that has a low parasitic capacitance.
Another object of the invention has been to provide a process for manufacturing said bonding pad.
These objects have been achieved by limiting the damascene wiring directly below the bonding pad to its outer edges, that is forming it in the shape of a hollow square. It is over-filled with a suitable soft metal (typically copper or one of its alloys) and then planarized in the usual way. After a passivation layer, including suitable diffusion barriers, has been laid over the structure, a via hole for communicating with the damascene wiring is then formed. This via can take the shape of a somewhat smaller hollow square or it can be formed from a series of individual vias arranged in the shape of a broken hollow square.


REFERENCES:
patent: 5149674 (1992-09-01), Freeman, Jr. et al.
patent: 5284797 (1994-02-01), Heim
patent: 5661081 (1997-08-01), Hsue et al.
patent: 5700735 (1997-12-01), Shine et al.
patent: 5834365 (1998-11-01), Ming-Tsung et al.
patent: 5939335 (1999-08-01), Arndt et al.
patent: 6124198 (2000-09-01), Moslehi
patent: 6143646 (2000-11-01), Wetzel
patent: 6163074 (2000-12-01), Lee et al.
patent: 6184141 (2001-02-01), Avanzino et al.
patent: 6198170 (2001-03-01), Zhao
patent: 6245683 (2001-06-01), Liu

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