bonded wafer processing

Fishing – trapping – and vermin destroying

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437 63, 437 64, 437 67, 148DIG50, H01L 2176

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057803110

ABSTRACT:
Warpage in a bonded wafer is limited by maintenance of a stress compensation layer on the backside of the bonded wafer during device fabrication processing. One embodiment applies a sacrificial polysilicon layer over a stress compensation silicon dioxide layer for bonded silicon wafers. The fabrication processing consumes the polysilicon layer but not the stress compensation silicon dioxide.

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Patent Abstract of Japan, vol. 13, No. 38 (E-709), Japanese Application No. 63-237408, (Sumitomo Metal Mining Co., LTD) Jan. 27, 1989.
S. Wolf, "Silicon Processing for the VLSI ERA", vol. 1, pp. 532-534, Jun. 1987.

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