Bonded wafer processing

Details Bonded wafer processing Bonded wafer processing

1997-04-14

1998-09-01

Dang, Trung

Semiconductor device manufacturing: process

Bonding of plural semiconductor substrates

Warping of semiconductor substrate

438406, 438455, 438459, 148DIG12, H01L 2146

Patent

active

058010840

ABSTRACT:
Warpage in a bonded wafer is limited by maintenance of a stress compensation layer on the backside of the bonded wafer during device fabrication processing. One embodiment applies a sacrificial polysilicon layer over a stress compensation silicon dioxide layer for bonded silicon wafers. The fabrication processing consumes the polysilicon layer but not the stress compensation silicon dioxide.

REFERENCES:
patent: 4985745 (1991-01-01), Kitahara et al.
patent: 5071785 (1991-12-01), Nakazato et al.
patent: 5113236 (1992-05-01), Arnold et al.
patent: 5183783 (1993-02-01), Ohta et al.
English translation of JP 01-302740; pp. 1-14, Dec. 6, 1989.
Wolf; "Silicon Processing for the VLSI Era"; 1986; pp. 532-534.
Patent Abstract of Japan, vol. 13, No. 38 (E-709) Japanese Application No. 63-237408, (Sumitomo Metal Mining Co., Ltd.) Jan. 27, 1989.
IEEE Transactions on Electron Devices, vol. 38, No. 7, Jul. 1991, New York U.S. pp. 1650-1654, A. Nakagawa et al., "Breakdown Voltage Enhancement for Devices on thin Silicon Layer/Silicon Dioxide Film".

Affiliated with

Also associated with

Rating

Bonded wafer processing does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Bonded wafer processing, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Bonded wafer processing will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-269830