Bonded sapphire polygon shield

Details Bonded sapphire polygon shield Bonded sapphire polygon shield

2001-11-07

2003-08-12

Pert, Evan (Department: 2829)

Semiconductor device manufacturing: process

Chemical etching

Vapor phase etching

C204S298010, C204S298110, C118S504000, C438S800000

Reexamination Certificate

active

06605544

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates to semiconductor manufacturing. More specifically, the present invention relates to bonded sapphire polygonal shields for providing contamination control during silicon wafer processing.
BACKGROUND OF THE INVENTION
It is critical that the fabrication of semiconductor devices, such as Very Large Scale Integrated (VLSI) and Ultra Large Scale Integrated (ULSI) circuits, takes place on silicon substrates having very high crystalline perfection or purity. Very high crystalline perfection requires that the silicon substrate possess a minimum of impurities and structural defects throughout its single crystal silicon lattice.
Generally during semiconductor manufacturing, raw material, e.g., quartzite, is refined into electronic grade polysilicon (EGS) and melted. A silicon seed crystal is than used to grow a single crystal silicon ingot from the molten EGS. The ingot is then precisely sliced and polished into silicon wafers. The silicon wafers provide the substrates upon which VLSI and ULSI circuits are ultimately built through a complex sequence of wafer fabrication processes.
However, many of these fabrication processes take place in process chambers under extreme conditions, such as those found in high-temperature, high-pressure or harsh chemical environments. Problematically, these extreme conditions can erode the chamber walls, causing severe contamination problems. Examples of such processes and their associated contamination problems include the following:
During Physical Vapor Deposition (PVD), plasma is used to sputter a target material onto a wafer. However, the process chamber (typically aluminum) may be sputtered off and contribute to the contamination of the wafer being processed.
Etching processes utilize various chemistries to etch features into the wafer. These chemistries often break down materials present in the process chamber which can potentially contaminate the wafer being etched.
During Ion Implantation processes stray ions may react with surrounding chamber walls causing unwanted reactions which can further contaminate a wafer.
Prior art structures for addressing the problems of contamination control include coated chamber walls or chamber walls constructed out of materials which match the wafer materials being processed, e.g. silicon. However, these structures do not eliminate the contamination process, but rather provide a sympathetic contaminant that can be tolerated by the wafers being processed. Additionally, the construction of these specialized chambers is excessively expensive. Moreover, their use is limited to processing only those wafers having material compatible with the chamber walls.
Additionally, prior art structures or shields designed to protect the silicon wafers from contamination must also be able to withstand high temperature processing of the wafers without damage. However, if a shield were to be constructed with materials having different coefficients of expansion, the shields may crack or shatter. Even structures composed entirely of a single crystal material will encounter problems with different coefficients of expansion along the different lattice planes of the crystal.
Based on the foregoing, it is the general object of the present invention to provide a structure that overcomes the problems and drawbacks associated with prior art contamination control structures.
SUMMARY OF THE INVENTION
The present invention offers advantages and alternatives over the prior art by providing in a first aspect a shield for protecting silicon wafers. The shield includes a plurality of single crystal shielding members having a lattice unit cell repeated substantially throughout. The unit cell has a periodic arrangement of atoms defining a set of lattice planes. The shielding members each include a pair of first interface surfaces having an orientation substantially aligned along one of the set of lattice planes. The shield also includes a plurality of single crystal structural members each having substantially the same lattice unit cell as that of the shielding members repeated substantially throughout. The structural members each include a pair of second interface surfaces having an orientation substantially aligned along the same one of the set of lattice planes. The plurality of shielding members and structural members are alternately bonded together at their respective first and second interface surfaces to define an enclosed area sized to receive the silicon wafers therein.
In an alternative embodiment of the invention, the orientations of the lattice planes of the shield are defined by a set of miller indices. The first and second interface surfaces have orientations substantially defined by an identical one of the set of miller indices.
In another embodiment of the invention, the shielding members are composed of sapphire plates. Additionally the structural members are composed of sapphire bars and/or sapphire rods.
In another embodiment of the invention, the shielding members and structural members are bonded together with a eutectic bonding material. The eutectic bonding material may also include a yttrium-containing compound.


REFERENCES:
patent: 5201977 (1993-04-01), Aoshima
patent: 6012303 (2000-01-01), Axelson et al.

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