Semiconductor device manufacturing: process – With measuring or testing
Reexamination Certificate
2002-01-30
2003-08-05
Thompson, Craig (Department: 2813)
Semiconductor device manufacturing: process
With measuring or testing
Reexamination Certificate
active
06602726
ABSTRACT:
FIELD OF THE INVENTION
This invention relates generally to integrated circuit manufacturing and more specifically to a wire-bonding step in the manufacture of an integrated circuit package.
BACKGROUND OF THE INVENTION
As illustrated in
FIG. 1
, an integrated circuit chip
2
is electrically connected to the outside world by connecting a wire
4
(typically called bond wire) from electrical contact points
6
, commonly called bond pads, on the chip
2
to electrical contact points, commonly called bond surfaces,
8
on a physical support structure
10
. Conductive traces
12
on the support structure then carry electrical signals to and from the chip to other components of the electrical circuit in which the chip is placed. Typically, the traces and bond surfaces are formed of a thick film when the support structure is, e.g., a ceramic substrate, which thick film is subject to heat in order to cure it. In applications where the support structure is a flexible film, thin films are more commonly employed for the conductive traces and, bond surfaces.
The integrated support structure
10
may be a lead frame in some applications, which is subsequently encapsulated in a package, such as for instance, by being placed in an injection mold and surrounded by a plastic encapsulation that electrically insulates and environmentally protects the chip, forming an IC package. Electrical contact to the chip can be made via the lead frame, which extends beyond the package. The finished package is then mounted onto a circuit board to form part of a desired electrical circuit. In many applications, the lead frame comprises a thin, flexible film, such as polyemide, upon which is formed a thick film layer that is patterned to form the electrical traces
12
. Ball grid array packages are a common example.
In other applications, the integrated circuit chip
2
is mounted directly onto the substrate or circuit board, without the need for a leadframe. In such an application, the circuit board itself provides the support structure
10
. Typically, the circuit board is a ceramic substrate upon which a thick film is formed and patterned to form the electrical traces
12
. One example of such an application is a multi-chip module in which several integrated circuit chips are mounted on a common substrate and connected together before being encapsulated. Another example is the commonly called hybrid circuit in which several integrated circuit chips are mounted directly onto a ceramic substrate (e.g., an alumina substrate) and electrically connected together by conductive traces
12
on the substrate forming support structure
10
. Typically, the entire substrate is then encapsulated in order to electrically isolate and environmentally protect the integrated circuit chips.
Regardless of the application, the bond pads
6
on the chip must be electrically connected to bond surfaces
8
on the support structure. This is typically accomplished by connecting a thin wire, typically gold, between the bond pads and the bond surfaces, in a process referred to as wire bonding. In most applications, the bond wire is relatively thin, on the order of 15-33 &mgr; in diameter (although the teachings of the present invention is not limited by the size, type or composition of the bond wire). Typically, the wire is welded from the bond pad on the chip to a bond surface on the support structure in a process referred to as wire bonding. Any type of suitable bond may be made at either the bond pads or the bond surfaces, including ball bonds, stitch bonds, and the like. The weld is typically performed using well know techniques such as thermosonic, ultrasonic, compression, and the like. A ball bond may be used, for example, at the bond pad and a stitch bond may be used, for example, at the lead.
In many applications, the bond pads are also relatively small, on the order of 2 mils to 10 mils square, although the teaching of the present invention applies to larger as well as smaller bond surfaces. Likewise, the bond surface is also generally on the order of several mils in size. Because the conductive traces
12
, including the bond surfaces
8
, are commonly formed from a thick film, the bond surface of the bond surfaces (that is the surface to which the bond wire will be attached) is subject to deformation—particularly during the bake process by which the conductive traces are cured after being formed on the support structure
10
. Materials such as gold, copper, nickel based alloys, aluminum, tungsten, copper-clad materials, and other well known alternatives are typically employed for the conductive traces and bond surfaces.
FIG. 2
illustrates in cross section a bond surface
8
that has deformed during the bake process. Note that, due to surface tension and shrinking, the top of the bond surface has taken on a pronounced radius of curvature and that as a result, the width of the bond surface has been reduced somewhat. Dotted lines
14
indicate the width of the lead surface
8
prior to shrinkage. As shown, the actual surface available for placement of a ball bond, stitch bond, or the like, is significantly reduced after shrinkage—in some instances the width shrinks to 90% or less of the pre-shrinkage surface area. In addition, the radius of curvature of the lead surface also provides a less ideal surface of bonding to than the ideal flat surface illustrated by dotted line
15
. Both of these are deviations from the ideal bond surface, (i.e. shrinkage and radius of curvature) can result in the bond wire being mis-aligned to the bond surface or an incomplete or unsatisfactory bond between the bond wire and bond surface. Device failure, performance degradation, and reliability problems can result from such a situation.
In the past, device manufacturers have simply tried to minimize the effects of bond surface deformation through selection of the lead material and/or control over the heat processing of the device. This constraints limit the flexibility and adaptability of the manufacturing process, however. Other past attempts to correct the problem have involved an operator manually pressing down on individual bond surfaces with a tool to attempt to flatten the leads. This process is labor-intensive, time consuming, and subject to wide process variations; it is not a practical solution for high volume, inexpensive, high reliability manufacturing.
It has been known in the past to employ a clamping device to hold lead frames in place during, e.g., the wire bonding process. Lead frames, upon which the bond surface may be found, are typically small, thin components, generally metallic, and are typically in the form of small fingers extending from a central location near the chip outward to a surface to be connected to a circuit board. The lead frame fingers are subject to damage and misplacement during the bonding process. Commonly owned U.S. Pat. No. 6,322,659, issued Nov. 27, 2001 and entitled “System and Method for Dual Head Bonding,” which patent is incorporated herein by reference, teaches such a method and apparatus for clamping lead frames in place during the bonding process.
Regardless of how lead frames are dealt with during the bonding process, what is needed is a method and apparatus that can quickly, reliably, and inexpensively condition a bond surface, particularly a thick film surface, to prepare the surface for reliable wire bonding. What is also needed is a method and apparatus that can be readily integrated into existing manufacturing processes.
SUMMARY OF THE INVENTION
The above shortcomings of the prior art are overcome and novel contributions to the art are provided by the preferred embodiments of the present invention. In one aspect, the invention provides for a method of conditioning the bond surfaces of a support structure by aligning the support structure within a clamp such that the bond surfaces on the support structure are aligned with raised boss surfaces on the clamp surface. The clamp is then brought into forcible contact with the support structure such that the raised boss surfaces on the clamp conta
Malolepszy Sean Michael
Sakakini Peter J.
Brady III Wade James
Telecky , Jr. Frederick J.
Texas Instruments Incorporated
Thompson Craig
LandOfFree
Bond surface conditioning system for improved bondability does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Bond surface conditioning system for improved bondability, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Bond surface conditioning system for improved bondability will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3101239