Bond pads using mesh pattern via structures for protecting...

Details Bond pads using mesh pattern via structures for protecting... Bond pads using mesh pattern via structures for protecting...

2001-05-17

2003-04-22

Nelms, David (Department: 2818)

Active solid-state devices (e.g., transistors, solid-state diode

Combined with electrical contact or lead

Of specified material other than unalloyed aluminum

C257S750000, C257S760000, C438S622000, C438S624000

Reexamination Certificate

active

06552433

ABSTRACT:

BACKGROUND OF THE INVENTION
(1) Field of the Invention
The present invention relates generally to semiconductor integrated circuit processing and more particularly to contact pad structures that resist intermetal dielectric (IMD) cracking and also to structures that increase circuit density on integrated circuit chips.
(2) Description of Prior Art
Trends toward increased circuit density and complexity in modern integrated circuit design have resulted in the requirement for significant increases in the number of input/output and power/ground pins per chip and the number of bond pads in order to connect to the package. To conserve active device area it is necessary to reduce the bond pad pitch. However, smaller bond pads are more easily damaged by the large mechanical stresses inherent in the bonding operation. Moreover, flip-chip packaging techniques with an area array are utilized to achieve the required high density of interconnection, which moves input/output bond pads from the periphery to positions in the vicinity of active areas. Generally, design rules have not allowed bonding pads over active areas, where they would be susceptible to damage from the large mechanical stresses of bonding. It is therefor required to devise structures and layouts that would satisfy the high-density requirements of advanced integrated circuit design and that would resist the high mechanical stresses of bonding.
Fujiki et al. in U.S. Pat. No. 5,736,791, discloses bonding pad structures, utilizing via holes, which resist cracking. Sato, U.S. Pat. No. 5,739,587, discloses bonding pad structures containing via holes, or grooves, which prevent moisture from entering devise areas. Bond pad structures that contain via holes and provide for reliable interconnections are disclosed by Shiue et al in U.S. Pat. Nos. 5,700,735 and 5,923,088. Yu in U.S. Pat. No. 6,028,367 discloses bond pads equipped with heat dissipating rings and containing via holes.
Bonding pads are the interfaces between the integrated circuits contained in semiconductor chips and the chip package. A large number of bonding pads is required to transmit power/ground and input/output signals to the chip devices. It is thus important that the bonding pad yield be sufficiently high to ensure a high per chip yield.
The general bonding pad structure consists of metal layers, emanating from the terminals of the chip devices, separated by intermetal dielectric (IMD) layers that are often silicon oxide. An IMD layer separates the uppermost metal layer from a bonding metal pattern that is formed over this IMD layer. Metal vias pass through the IMD layers connecting the metal layers to the bonding metal pattern. Wires are bonded to the bonding metal pattern and to the chip package forming electrical connections between the chip and the package. A passivation layer covers the surface, except over the bonding sites, to seal the chip from contaminants and for scratch protection.
An important failure mode involves cracking of the IMD. Referring to
FIG. 1
, there is shown a conventional via hole array. Region
10
is an IMD layer and regions
12
are metal filled via holes passing through the IMD. Cracks that are observed in the IMD are similar to that,
14
, depicted in FIG.
2
. These are cracks that propagate along the IMD layer avoiding the metal of the vias. Once a small crack is initiated it will, under stresses prevalent during processing, grow extensively.
To avoid problems in devices that could arise from bonding mechanical stresses design rules do not allow devices to underlie bonding pads. Therefor the situation is as depict in
FIGS. 3 and 4
, where chip areas under bonding pads are not utilized. In
FIG. 3
there is shown a conventional bonding pad structure containing a multiplicity of metal levels,
16
, separated by IMD levels,
10
, through which pass metal filled via holes,
12
. The arrow,
18
, represents bonding mechanical stresses because of which devices, represented by the schematic
20
, are not situated in the area under the bonding pad. This structure where the bonding pad and device occupy adjacent areas is denoted a horizontal structure. Thus chip area is thus underutilized in a horizontal structure, and this is to avoid problems that could arise from bonding mechanical stresses. A similar conventional bonding pad structure is shown in
FIG. 4
, where the horizontal components in this case are the bonding pad structure and devices to guard against electrostatic discharge, or ESD structures,
22
. There is an added problem with ESD structures concerning optimization of chip area utilization. Whereas integrated circuit devices can be scaled down aggressively, this is not the case for ESD structures, which cannot be shrunk without sacrificing the to some extent the ability of the ESD structures to protect core circuits during packaging and handling. Again the horizontal structure underutilizes the chip area and in this case aggressive down scaling cannot be accomplished without paying the price of reduced ESD protection.
SUMMARY OF THE INVENTION
It is a primary objective of the invention to provide a new bonding pad structures that are immune to IMD cracking, withstanding even the stresses encountered during chip packaging and that does not allow transmission of damaging stress beyond the bonding pad structure. It is also a primary objective of the invention to disclose a new vertical structure in which devices can occupy chip area underlying new bonding pad structures, greatly improving the utilization of chip area. Novel mesh pad structures are proposed that increase bonding pad strength, eliminate extensive cracking of the IMD, and do not transmit damaging stress, originating from the bonding process, to underlying chip areas. Instead of traditional via holes, extended parallel trenches, filled with metal are formed through the IMD, with trenches of successive levels crisscrossing. The metal trenches form a mesh pattern that together with the metal layers effectively enclose the dielectric of the IMD layer into small cells surrounded by metal. This increases the strength of the bonding pad so that IMD cracking is less likely to occur. Furthermore, even in the unlikely event of the initiation of an IMD crack, the crack will propagate no further than the metal trench. Additionally the extensive metal mesh pattern can readily distort, thus relieving stress. It has been determined that whereas high, damaging stresses, originating in bonding, are found to extend to the chip area under conventional bonding pads, for bonding pads according to the invention high, damaging stresses do not penetrate to the underlying chip area. Therefor the chip area under bonding pads fabricated according to the invention, not being subject to high mechanical stress, is available for devices and, in particular, for ESD structures.
A vertical structure and a method of forming a vertical structure are disclosed. A partially processed semiconductor wafer is provided having all devise levels completed, including a topmost interlevel dielectric layer through which metallic vias are formed for electrical connection. A first metal level is formed. An IMD level is then formed by forming a blanket dielectric layer over the first metal level, patterning and etching the dielectric layer to form arrays of trenches passing through the dielectric layer, filling the trenches with a conducting material, and performing CMP. A number of metal level, IMD level pairs are formed, where the number could be zero. Bonding metal patterns are deposited, wires are bonded onto the bonding metal patterns and a passivation layer is formed.


REFERENCES:
patent: 5700735 (1997-12-01), Shiue et al.
patent: 5736791 (1998-04-01), Fujiki et al.
patent: 5739587 (1998-04-01), Sato
patent: 5891799 (1999-04-01), Tsui
patent: 5923088 (1999-07-01), Shiue et al.
patent: 6028367 (2000-02-01), Yu
patent: 6143396 (2000-11-01), Saran et al.
patent: 6180511 (2001-01-01), Kim et al.
patent: 6251781 (2001-06-01), Zhou et al.
Liang et al. U.S. patent application Publication No. 2001/0045669, fi

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