Bolometric focal plane array

Radiant energy – Invisible radiant energy responsive electric signalling – Infrared responsive

Reexamination Certificate

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Details

C250S332000, C250S370080

Reexamination Certificate

active

06249002

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The invention relates to a bolometric focal plane array and more particularly to a bolometric focal plane array having an integrated signal processor for processing signals from an array of bolometer detectors.
2. Discussion of the Related Art
Thermal radiation detectors that operate at room temperature have been known for more than 100 years. Recently, the availability of integrated circuit and micromachining technology has revived interest in this field. It is now practical to manufacture an array containing many thousands of these detectors along with signal processing electronics.
A bolometer is a thermal radiation detector that operates by first absorbing incident electromagnetic radiation and converting the absorbed energy into heat. The resulting temperature change of the detector is then sensed by measuring its resistance, which is a function of temperature. In a large array of such detectors, it is practical to measure the resistance of only a few detectors at any given time without compromising the signal to noise ratio of the system. The signal to noise ratio is a very important parameter for practical systems.
As a result, there remains the problem of how to implement circuitry to measure the resistance of many thousands, for example more than 80,000 detectors, within the size, power, and component restrictions placed upon an integrated circuit. The integrated circuitry must measure the resistance of each element of the array and format the results into a single data stream. The signal from each bolometer far exceeds the integrating capacity of a single practically sized integrated capacitor. It is therefor a motive of the invention to provide a bolometric focal plane array with an integrated signal processor that fits within a reasonable area, uses only the components available within the integrated circuit process, and dissipates a limited amount of power.
SUMMARY OF THE INVENTION
An infrared radiation detector apparatus of the present invention comprises a plurality of bolometric infrared detectors addressed by a plurality of column lines and a plurality of row lines. A plurality of electronic metal oxide semiconductor (MOS) switches each connects one of the plurality of bolometric infrared detectors between one of the plurality of row lines and one of the plurality of column lines. The plurality of bolometric infrared detectors and the plurality of electronic MOS switches are constructed on an integrated circuit. The bolometric infrared detectors may be micromachined into the integrated circuit.
In one aspect of the invention, the bolometric focal plane array of the invention comprises on-chip signal processing electronics and a plurality of bolometers. Each bolometer has an associated simulated detector. The simulated detector is used to test the on-chip electronics before the bolometer is created. This avoids the creation of bolometers on bad chips. The array is composed of 328×246 unit cells. Each unit cell contains a bolometer, associated electronics and a simulated detector. Each bolometer is accessible through a row and column scheme where the bolometers are found along a common column and addressed by separate row select lines. A row shift register selects the row and the bolometer signals are read out sequentially for each column. During a test mode the simulated detectors are individually accessed using a column shift register and a row shift register. The row shift register accesses a particular row and the column shift register accesses a particular colurnn so that a particular single simulated detector output can be sensed. The chip has a temperature sensor to determine whether the chip has exceeded its operational temperature. Each column has a buffered direct injection amplifier providing a signal to a detector integration node capacitor. The detector integration node capacitor provides a signal to a comparator that receives an input from a ramp generator.
During the operation of the invention control states are reset, and the digital ramp generator is held at a low value to allow the comparator to proceed to dump unit charges off the bolometer. Off chip there is a memory that stores the value of the counter for each row and column unit cell. Also off chip is a memory that stores a preset for the detector integration node capacitor for each row and column unit cell. Detector protection circuitry times out the circuit when the row select signal is not received from external sources within a predetermined time.
Each unit cell comprises a low resistance switch, gated in response to the row select line, that switches a detector signal to the resistance measuring circuitry. A reset is also included. The array of resistance measuring circuitry has few channels compared to the number of detector elements, typically one circuit for each row or each column in the detector array. The control circuitry supplies appropriate signals to the switches and to the resistance measuring circuitry.
Other objects, features and advantages of the present invention will become apparent to those skilled in the art through the description of the preferred embodiment, claims and drawings herein wherein like numerals refer to like elements.


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